Hardware Principle and Analysis
Pin Description
Pin Name |
Pin Function |
R/B(RnB) |
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. |
CLE(CLE) |
The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. |
CE(nFCE) |
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation. |
BUT(BUT) |
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. |
WE(nFWE) |
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. |
RE(nFRE) |
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. |
I/O(LDATA0-LDATA7) |
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled. |
Operate Nand Flash on U-BOOT
NAND FLASH S3C2440
Send command to select chip
CLE is set to high level NFCMMD = command value
Output command value on DATA0~DATA7
Send a write pulse
Send address to select chip NFADDR=address value
ALE is set high
Output address value on DATA0~DATA7
Send a write pulse
Send data to selected chip NFDATA=data value
ALE, CLE set to low level
Output data value on DATA0~DATA7
Send a write pulse
Read data and select chip val=NFDATA
Send out read pulse
Read data from DATA0 to DATA7
OpenJTAG> help md
md [.b, .w, .l] address [# of objects]
- memory display
OpenJTAG> help mw
mw [.b, .w, .l] address value [count]
- write memory
•b 1 byte
•W 2 bytes
• 4 bytes
1. Read ID
S3C2440 |
u-boot |
Select NFCONT bit1 and set it to 0 |
md.l 0x4E000004 1; mw.l 0x4E000004 1 |
Issue command 0x90 NFCMMD=0x90 |
mw.b 0x4E000008 0x90 |
Send address 0x00 NFADDR=0x00 |
mw.b 0x4E00000C 0x00 |
Read data to get 0xEC val=NFDATA |
md.b 0x4E000010 1 |
Read data to get device code val=NFDATA |
md.b 0x4E000010 1 |
Exit the ID reading state NFCMMD=0xff |
mw.b 0x4E000008 0xff |
2. Read content: read the data at address 0
Use UBOOT command:
nand dump 0
Page 00000000 dump:
17 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5
S3C2440 |
u-boot |
Select NFCONT bit1 and set it to 0 |
md.l 0x4E000004 1; mw.l 0x4E000004 1 |
Issue command 0x00 NFCMMD = 0x00 |
mw.b 0x4E000008 0x00 |
Send address 0x00 NFADDR=0x00 |
mw.b 0x4E00000C 0x00 |
Send address 0x00 NFADDR=0x00 |
mw.b 0x4E00000C 0x00 |
Send address 0x00 NFADDR=0x00 |
mw.b 0x4E00000C 0x00 |
Send address 0x00 NFADDR=0x00 |
mw.b 0x4E00000C 0x00 |
Send address 0x00 NFADDR=0x00 |
mw.b 0x4E00000C 0x00 |
Issue command 0x30 NFCMMD=0x30 |
mw.b 0x4E000008 0x30 |
Read data to get 0x17 val=NFDATA |
md.b 0x4E000010 1 |
Read data and get 0x00 val=NFDATA |
md.b 0x4E000010 1 |
Read data and get 0x00 val=NFDATA |
md.b 0x4E000010 1 |
Read data and get 0xea val=NFDATA |
md.b 0x4E000010 1 |
Exit read status NFCMMD = 0xff |
mw.b 0x4E000008 0xff |
The role of ECC
S3C2440-Nand Flash Controller Register
S3C2440-Nand Flash Memory Timing
K9F2G08U0C-Key Characteristic
K9F2G08U0C-Operation Timing
Drivers
driver.c
1 /*
2 * SAMSUNG: K9F2G08U0C
3 * 参考:
4 * .linux-2.6.22.6driversmtdnands3c2410.c
5 * .linux-2.6.22.6driversmtdnandat91_nand.c
6 */
7 #include
8 #include
9 #include
10 #include
11 #include
12 #include
13 #include
14 #include
15 #include
16 #include
17 #include
18
19 #include
20 #include
21 #include
22 #include
23
24 #include
25
26 #include
27 #include
28
29 struct regs_nand {
30 unsigned long NFCONF;
31 unsigned long NFCONT;
32 unsigned long NFCMMD;
33 unsigned long NFADDR;
34 unsigned long NFDATA;
35 unsigned long NFMECCD0;
36 unsigned long NFMECCD1;
37 unsigned long NFSECCD;
38 unsigned long NFSTAT;
39 unsigned long NFESTAT0;
40 unsigned long NFESTAT1;
41 unsigned long NFMECC0;
42 unsigned long NFMECC1;
43 unsigned long NFSECC;
44 unsigned long NFSBLK;
45 unsigned long NFEBLK;
46 };
47
48 static struct nand_chip *nand;
49 static struct mtd_info *mtd;
50 static struct regs_nand *regs_nand;
51
52 //分区信息
53 static struct mtd_partition nand_parts[] = {
54 [0] = {
55 .name = "bootloader",
56 .size = 0x00040000,
57 .offset = 0, /* offset within the master MTD space */
58 },
59
60 [1] = {
61 .name = "params",
62 .offset = MTDPART_OFS_APPEND, //紧跟着上一个分区的大小
63 .size = 0x00020000,
64 },
65
66 [2] = {
67 .name = "kernel",
68 .offset = MTDPART_OFS_APPEND, //Following the size of the previous partition
69 .size = 0x00200000,
70 },
71
72 [3] = {
73 .name = "root",
74 .offset = MTDPART_OFS_APPEND, //Following the size of the previous partition
75 .size = MTDPART_SIZ_FULL,
76 },
77 };
78
79 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
80 {
81 if (chipnr == -1)
82 {
83 //Uncheck: NFCONT[1]:0
84 regs_nand->NFCONT |= (1<<1);
85 }
86 else {
87 //Select: NFCONT[1]:1
88 regs_nand->NFCONT &= ~(1<<1);
89 }
90 return;
91 }
92
93 static void nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
94 {
95 if (ctrl & NAND_CLE)
96 {
97 //Send command :NFCMMD=dat
98 regs_nand->NFCMMD = dat;
99 }
100 else
101 {
102 //Sending address: NFADDR=dat
103 regs_nand->NFADDR = dat;
104 }
105 return;
106 }
107
108 static int nand_dev_ready(struct mtd_info *mtd)
109 {
110 return (regs_nand->NFSTAT & (1<<0));
111 }
112
113
114 /* 1 Entrance and exit functions*/
115 static int __init nand_init(void)
116 {
117 struct clk *clk;
118
119 /* 2 Allocate a nand_chip structure*/
120 nand = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
121 /******** 2 end ********/
122
123 regs_nand = ioremap(0x4E000000, sizeof(struct regs_nand));
124
125 /* 3 Setting: nand_chip */
126 //Provide: select, send command, send address, send data, read data, judge status function
127 nand->select_chip = nand_select_chip; //Chip select
128 nand->cmd_ctrl = nand_cmd_ctrl; //Send command
129 nand->IO_ADDR_R = ®s_nand->NFDATA; //Read
130 nand->IO_ADDR_W = ®s_nand->NFDATA; //Write
131 nand->dev_ready = nand_dev_ready; //Flash status (busy/idle)
132 nand->ecc.mode = NAND_ECC_SOFT; //ecc software check
133 /******** 3 end ********/
134
135 /* 4 Hardware related operations: timing*/
136 //Enable clock
137 clk = clk_get(NULL, "nand");
138 clk_enable(clk);
139
140 #define TACLS 0
141 #define TWRPH0 1
142 #define TWRPH1 0
143 //Time parameter setting
144 regs_nand->NFCONF = (TACLS<<12) | (TWRPH0<<8) | (TWRPH1<<4);
145
146 //Control---Enable nand flash controller, cancel chip select
147 regs_nand->NFCONT = (1<<0) | (1<<1);
148 /******** 4 end ********/
149
150
151 /* 5 Use: nand_scan */
152 mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
153 mtd->owner = THIS_MODULE;
154 mtd->priv = nand; //Private data
155
156 nand_scan(mtd, 1); //Identify nand_flash, construct mtd_info structure
157 /******** 5 end ********/
158
159
160 /* 6 Add partitions: add_mtd_partitions */
161 add_mtd_partitions(mtd, nand_parts, 4);
162
163 //No partitioning situation
164 //add_mtd_device(mtd);
165 /******** 6 end ********/
166
167 return 0;
168 }
169
170 static void __exit nand_exit(void)
171 {
172 del_mt d_partitions(mtd);
173 kfree(nand);
174 kfree(mtd);
175 iounmap(regs_nand);
176 return;
177 }
178
179 module_init(nand_init);
180 module_exit(nand_exit);
181 MODULE_LICENSE("GPL");
182 /******** 1 end ********/
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Next article:NOR Flash Driver
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