Xiaomei Ge’s FPGA introduction to practical special training class full HD record (2019)

This set of courses is a recorded course of Xiaomei’s field training class in 2019. It is rich in content, high in knowledge, and carefully edited, so the viewing experience is good.

The course content is arranged as follows:

Basic solidification stage (Lessons 1 to 21).

This stage mainly uses some simple examples of theoretical background knowledge as the basis for course development, allowing students to start with basic lighting and understand step by step how Verilog designs FPGA digital logic. Common methods and techniques. A few seemingly inadvertent experiments, according to the arrangement of our course content, you will find that by doing it, you will have mastered the core of the linear sequence machine and the design and use of the state machine. Everything was so natural, but it came naturally. Not only did I understand the principles and methods, but I also realized the advantages of these design methods and mastered the skills of using these design methods.

At the same time, this stage is also a debugging ability development stage. Through these not-too-difficult experiments and courses, students can gradually learn and practice how to use modelsim to simulate the designed code and how to debug it. In the eyes of many people, simulation is just a means to verify whether the results are correct. In fact, the greater role of simulation is to assist debugging. When the simulation results are not as expected, how to analyze the root cause of the problem and how to use simulation and debugging skills Find the problem.

System modeling stage (Lessons 22 to 42)

This stage uses simple but comprehensive examples to raise the issue of collaborative work between multiple modules, and how to design reasonable interfaces so that each module can correctly interact with Other modules communicate with each other and exchange data. When the system design encounters problems, how to analyze and debug them one by one.

The example strengthening stage (lessons 23 to 70)

starts from the implementation of I2C protocol, to the debugging of camera image collection and display system, to the implementation of simple image conversion algorithm, from the implementation of Gigabit Ethernet underlying protocol to the implementation of Ethernet image transmission. Organically combine protocols with strong practicability and rich knowledge points to realize a practical Ethernet image transmission system.

Applicable objects:

Suitable for undergraduates, graduate students, working students or engineers in electronic information, communications, mechanical electronics and other related majors. It is emphasized that it must be a group with the purpose of self-study.

Unsuitable people:

1. People who are in a hurry and want to get things done quickly in a few days. (Maybe there is such an expert in the world who can help you learn FPGA quickly in a few days, but at least Xiaomei does not have this ability)

2. People who just watch the videos and think that they can learn it, and are unwilling to practice according to the course arrangements. (The course shares knowledge and experience, but developing FPGA requires the ability to write code, verify and debug. How to transform knowledge and experience into abilities? There is no shortcut, just practice! Practice! Practice! Practice!) 3.

Endurance Poor: Those who are unwilling to persevere when encountering difficulties, unwilling to study, and unwilling to make breakthroughs. (FPGA learning inherently has a bottleneck period for breakthroughs. This bottleneck period is very difficult. Often a small project may take several days to debug, even rewrite, and self-study. It inherently lacks the necessary external constraints. If there are no more Perseverance, without the courage to challenge difficulties, it will be really difficult to learn).

4. Project requirements: I found that some of our series of tutorials just meet the project requirements. (This type of user has a strong purpose in learning, and only cares about what he needs, and has no time to take into account a lot of basic content and foreshadowing. As a result, he did not learn the previous ones and could not keep up with many subsequent knowledge points, which are related to other projects. (You can’t digest the lessons)

The master leads you in. It depends on the individual’s practice. When we hold on-site training classes, all the content we teach is recorded in the video. When you watch the video for self-study and participate in our offline training classes, you will hear and see exactly the same content. The trainees are in a centralized environment and study intensively within a concentrated period of time without any distractions. So after 7 weeks, everyone has learned and can write and debug code independently. The most difficult thing about offline self-study is persistence and concentration. Therefore, whether you can learn it depends not on how good the tutorial is, but on the determination and perseverance of the learner.

I hope everyone will study hard and ask questions if you have any.

• Chapter 1：Scientific FPGA development process (45 minutes and 27 seconds)

• Chapter 2：Verilog basic logic design and verification (31 minutes and 47 seconds)

• Chapter 3：Examples of Synthesizable and Unsynthesizable Grammar (17 minutes and 26 seconds)

• Chapter 4：[Question Answer] Verilog Basic Logic Design Experiment (18 minutes and 24 seconds)

• Chapter 5：Review of the previous day’s course content (6 minutes and 48 seconds)

• Chapter 6：Counter driver LED flashing example FAQ analysis plus modelsim practical skills (22 minutes and 35 seconds)

• Chapter 7：Design and use of reusable modules (parametric design) (18 minutes and 20 seconds)

• Chapter 8：Non-equal duty cycle signal generation method (12 minutes and 37 seconds)

• Chapter 9：Sequential pulse signal generation method (7 minutes and 23 seconds)

• Chapter 10：The difference between if else writing and case writing in the underlying logic implementation (6 minutes and 16 seconds)

• Chapter 11：Analysis of linear sequence model design method (32 minutes and 55 seconds)

• Chapter 12：Sequence sending logic design task key points review plus task upgrade (28 minutes and 28 seconds)

• Chapter 13：Sequence sending logic design key content analysis and testing framework (26 minutes and 20 seconds)

• Chapter 14：Analysis and HDL design of sequence loop transmission control logic state machine (39 minutes and 53 seconds)

• Chapter 15：UART serial port protocol receiving and serial port sending module design tasks (29 minutes and 8 seconds)

• Chapter 16：Review of key questions in serial port sending experiment (30 minutes and 31 seconds)

• Chapter 17：Introduction to key jitter phenomenon and solution analysis (37 minutes and 55 seconds)

• Chapter 18：Debugging Problem State Machines Using In-System-Sources-and Probe (31 minutes and 9 seconds)

• Chapter 19：Metastability problem principles and countermeasures (50 minutes and 16 seconds)

• Chapter 20：Explanation of common syntax for simulation 1 (30 minutes and 18 seconds)

• Chapter 21：Serial port receiving design key points and FAQs (48 minutes and 54 seconds)

• Chapter 22：Introduction to data acquisition and transmission system architecture (25 minutes and 29 seconds)

• Chapter 23：Application principle of TLV5618 DAC with SPI interface (38 minutes and 23 seconds)

• Chapter 24：Key points of TLV5618 DAC drive logic design (31 minutes and 24 seconds)

• Chapter 25：Analysis of ADC128S052 device interface and driver design based on SPI interface (57 minutes and 27 seconds)

• Chapter 26：fifo memory role and structure model (21 minutes and 7 seconds)

• Chapter 27：Introduction and simulation test of fifo IP core in Quartus (43 minutes and 59 seconds)

• Chapter 28：ADC acquisition FIFO cache UART sending system task description (16 minutes and 40 seconds)

• Chapter 29：Practical operation of drawing data transmission control state transition diagram (20 minutes and 44 seconds)

• Chapter 30：Data transmission control state machine timing diagram drawing practice (37 minutes and 9 seconds)

• Chapter 31：Explanation of ROM usage and debugging in FPGA design (43 minutes and 0 seconds)

• Chapter 32：Data collection and transmission system bug debugging case (49 minutes and 28 seconds)

• Chapter 33：SPI timing review (11 minutes and 15 seconds)

• Chapter 34：Basic principles of I2C protocol (1 hours and 7 minutes and 11 seconds)

• Chapter 35：Principle and implementation of three-state open-drain mode of I2C SDA signal (43 minutes and 23 seconds)

• Chapter 36：I2C controller design points (29 minutes and 41 seconds)

• Chapter 37：IIC protocol single-byte transmission state machine design ideas (36 minutes and 32 seconds)

• Chapter 38：I2C controller top-level logic design ideas (42 minutes and 4 seconds)

• Chapter 39：Difficult case analysis_I2C bus response bit SDA cannot be pulled high (14 minutes and 38 seconds)

• Chapter 40：Summary of error-prone and easily overlooked points during I2C system debugging (15 minutes and 41 seconds)

• Chapter 41：Serial port reading and writing I2C interface EEPROM memory project analysis (49 minutes and 7 seconds)

• Chapter 42：A brief summary of the I2C project (2 minutes and 15 seconds)

• Chapter 43：Comparative understanding of camera SCCB protocol and I2C protocol (55 minutes and 56 seconds)

• Chapter 44：Migration of I2C controller to SCCB protocol (8 minutes and 31 seconds)

• Chapter 45：Comparison of SCCB and I2C protocols (supplementary enhanced explanation) (5 minutes and 38 seconds)

• Chapter 46：Camera data stream DVP interface protocol (41 minutes and 35 seconds)

• Chapter 47：I2C controller camera initialization key points guide (22 minutes and 58 seconds)

• Chapter 48：Camera register initialization experimental task (12 minutes and 47 seconds)

• Chapter 49：Camera DVP interface data receiving method and implementation (46 minutes and 2 seconds)

• Chapter 50：DVP interface logic coding demonstration and analysis of common anomalies (56 minutes and 2 seconds)

• Chapter 51：Analysis of Frequently Asked Questions in VGA Controller Experiments (12 minutes and 50 seconds)

• Chapter 52：Design of multi-resolution adaptive VGA controller using conditional compilation method (29 minutes and 41 seconds)

• Chapter 53：Use our website to help you solve common problems (4 minutes and 17 seconds)

• Chapter 54：Analysis on the principle of converting RAW data stream to RGB888 image data (31 minutes and 7 seconds)

• Chapter 55：Use a shift register to register a row of data (33 minutes and 51 seconds)

• Chapter 56：The relationship between storage bandwidth and RAW2RGB algorithm implementation location (5 minutes and 55 seconds)

• Chapter 57：RAW data flow RGB888 image key enhancement supplementary explanation (21 minutes and 48 seconds)

• Chapter 58：RAW2RGB logic simulation and debugging method (24 minutes and 16 seconds)

• Chapter 59：Summary of knowledge points of image acquisition and display system project (22 minutes and 19 seconds)

• Chapter 60：Introduction to basic concepts of Ethernet and MAC layer protocols (27 minutes and 4 seconds)

• Chapter 61：MAC layer data transmission interface MII_GMII_RGMII (25 minutes and 55 seconds)

• Chapter 62：Ethernet MAC layer board-level debugging method (12 minutes and 44 seconds)

• Chapter 63：Detailed explanation of Ethernet IP layer protocol (42 minutes and 18 seconds)

• Chapter 64：Detailed explanation of UDP protocol (19 minutes and 32 seconds)

• Chapter 65：Summary of Ethernet transmission projects (15 minutes and 32 seconds)

• Chapter 66：Introduction and key points analysis of image transmission system design based on Ethernet (53 minutes and 59 seconds)

• Chapter 67：Camera data capture and insert line number timing scheme (37 minutes and 8 seconds)

• Chapter 68：Summary of Ethernet image transmission project (29 minutes and 38 seconds)

• Chapter 69：Basic principles and methods of timing constraints (1 hours and 19 minutes and 47 seconds)

• Chapter 70：Basic concepts of timing analysis (1 hours and 29 minutes and 4 seconds)