The memory space of S3C2440 is divided into different blocks. When the CPU sends an address to the memory controller, the memory controller sends the corresponding chip select signal to the chip select pin according to the address range to realize the control of different devices.
BANK0 BUS WIDTH
The data bus of BANK0 (nGCS0) should be configured with a width as one of 16-bit and 32-bit ones. Because the BANK0 works as the booting ROM bank (map to 0x0000_0000), the bus width of BANK0 should be determined before the first ROM access, which will depend on the logic level of OM[1:0] at Reset.
MEMORY (SROM/SDRAM) ADDRESS PIN CONNECTIONS
Memory Interface with 8-bit ROM
Memory Interface with 8-bit ROM x 2
Memory Interface with 8-bit ROM x 4
Memory Interface with 16-bit ROM
Memory Interface with 16-bit SRAM x 2
analyze:
Take "Memory Interface with 16-bit ROM" as an example:
The CPU is byte-addressable; the ROM with a bit width of 16 is half-word-addressable (a half-word is equal to two bytes);
Which address line of the CPU is connected to A0 is determined by the data bit width of the memory chip. Since this ROM is addressed by halfword, the CPU should perform address conversion when accessing this ROM.
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