Introduction and measurement of edge trigger and level trigger of 51 single chip microcomputer

There are two triggering modes for the external interrupt of the 51 MCU: level triggering and edge triggering. When level triggering is selected, the MCU checks the interrupt source line in each machine cycle. When a low level is detected, the interrupt request flag is set and the CPU is requested to interrupt. When edge triggering is selected, the MCU detects that the interrupt source line is high in the previous machine cycle and detects a low level in the next machine cycle, i.e., the interrupt flag is set and the interrupt is requested.

This principle is easy to understand. However, there are a few points that require special attention when applying it:

1) In level-triggered mode, the interrupt flag register does not latch the interrupt request signal. In other words, the microcontroller directly assigns the level logic of the external interrupt source line sampled by S5P2 in each machine cycle to the interrupt flag register. The flag register is transparent to the request signal. In this way, when the interrupt request is blocked and not responded to in time, it will be lost. In other words, in order for the level-triggered interrupt to be responded to and executed by the CPU, it is necessary to ensure that the low level of the external interrupt source line is maintained until the interrupt is executed. Therefore, when the CPU is executing an interrupt of the same level or a higher level, if the external interrupt source (generating a low level) is cancelled (changed to a high level) before the interrupt is executed, it will not be responded to, just like it did not happen. Similarly, when the CPU is executing an instruction that cannot be interrupted (such as RETI), the level-triggered interrupt generated will not be executed if the time is too short.

2) In edge-triggered mode, the interrupt flag register latches the interrupt request. A high-to-low jump on the interrupt port line will be recorded in the flag register until the CPU responds and turns to the interrupt service routine, and then it is automatically cleared by the hardware. Therefore, when the CPU is executing a same-level interrupt (even an external interrupt itself) or a high-level interrupt, the generated external interrupt (negative jump) will also be recorded in the interrupt flag register. After the interrupt exits, it will be responded to and executed. If you don't want this, you must manually clear the external interrupt flag before the interrupt exits.

3) The interrupt flag can be cleared manually. If an interrupt is cleared manually before being responded to, the interrupt will be ignored by the CPU, just as if it had not occurred.

4) The choice of level trigger or edge trigger should be based on the purpose of the system using external interrupts, rather than based on the characteristics of the interrupt source signal as many materials say. For example, some books say ("Keil C51 Usage Skills and Practice"), which has a similar point of view.

The MCS51 microcontroller series is an 8-bit microcontroller . It was launched by Intel in 1980 after the successful design of the MCS48 series. Since the MCS51 series has strong on-chip functions and instruction systems, the application of microcontrollers has taken a leap forward, and this series of products soon became the world's second-generation standard controller. The 51 series microcontrollers have 5 interrupt sources, 2 of which are external input interrupt sources INT0 and INT1. The interrupt triggering mode of external input interrupt 1 and interrupt 0 can be controlled by IT1 (TCON.2) and IT0 (TCON.1) of the interrupt control register TCON respectively. If it is 0, the external input interrupt control is level-triggered; if it is 1, it is edge-triggered. Here is a falling edge-triggered interrupt.

1. Problem statement

Almost all domestic MCU materials have unclear or incorrect definitions of the response time of MCU edge-triggered interrupts. For example, the description of the response time of edge-triggered interrupts in document [1] is "For the pulse trigger mode (i.e. edge trigger mode), the level must be detected twice. If the first level is high and the second level is low, it means that a negative jump valid interrupt request signal is detected", but the actual situation is not the case.

We know that the interrupt trigger level of the microcontroller's external input is TTL level. For TTL level, the allowable range of the high level output of the TTL logic gate is

The allowable range of the output low level is 0~0.7 V, and its nominal value is 0.3 V[2]. The level between 0.7 V and 2.4 V is an intermediate level that is neither high nor low.

Thus, in practical applications, assuming that the MCU external interrupt pin INT0 inputs a falling edge signal from +5 V to 0 V, the MCU samples the INT0 pin in a certain clock cycle to obtain a high level of 2.4 V; and when the next clock cycle arrives for sampling, since it often takes a certain amount of time for the actual external input interrupt trigger signal to change from high level to low level, the detected level may not be a true low level (less than 0.7 V), but an intermediate level between low level and high level, that is, a level between 0.7 and 2.4 V. In this case, will the MCU still set the interrupt trigger flag to cause an interrupt? Regarding this point, most domestic textbooks and device information provided by MCU manufacturers do not give an accurate definition, but this situation does occur in practical applications.

Take the operational amplifier chip AD708 produced by Analog Corporation of the United States as an example. Its slew rate is 0.3 V/μs. In the comparator circuit composed of the AD708 chip, the falling edge of its output square wave drops from 2.4 V to 0.7 V, and the time required is about: (2.4 V-0.7 V)/0.3V·μs-1=4.67 μs. That is, it takes about 4.67 μs of transition time for the falling edge to actually drop from a high level to a low level. In actual application circuits, this falling time can often reach more than 10 μs. For a precise measurement system, such a long uncertainty time is unacceptable. Therefore, it is necessary to accurately measure the triggering moment of the microcontroller edge interrupt.