AMD launches second-generation Versal Premium series: FPGA industry's first to support CXL 3.1 and PCIe Gen 6

Technology media techpowerup published a blog post yesterday (November 12), reporting that AMD announced the second-generation Versal Premium series adaptive SoC platform, which will become the first device in the FPGA industry to use CXL3.1 and PCIe Gen6 in hard IP and support LPDDR5 memory.

High-speed data access and processing

The second-generation Versal Premium series adaptable SoC platform enables industry-leading high-bandwidth host CPU-to-accelerator connectivity by supporting CXL 3.1 and PCIe Gen 6, the industry's fastest host interfaces.

PCIe Gen 6 offers 2x to 4x line rates compared to FPGAs supporting PCIe Gen 4 or Gen 5, while CXL 3.1 running PCIe Gen 6 offers double the bandwidth of CXL 2.1 devices at similar latency, along with enhanced fabric and coherency features.

Improve memory bandwidth and utilization

The 2nd Gen AMD Versal Premium Series Adaptable SoCs accelerate memory bandwidth with the fastest LPDDR5 memory connection of up to 8533 Mb/s, enabling faster data transfers and real-time responses. This ultra-fast enhanced DDR memory can increase host connection speeds by up to 2.7 times compared to similar devices using LPDDR4/5 memory.

Connecting with CXL memory expansion modules can increase total bandwidth by up to 2.7 times compared to using LPDDR5X memory alone.

As a result, the second-generation Versal Premium series allows for scalable memory pooling and expansion for multiple accelerators, optimizing memory utilization and increasing bandwidth and capacity.

The second-generation Versal Premium series adaptable SoCs are designed to improve memory utilization in multi-head single logic devices (MH-SLDs) by dynamically allocating memory pools for multiple devices, enabling them to operate without fabric or switches while supporting up to two CXL hosts.

Strengthening data security

Enhanced security features help the second-generation Versal Premium family move data quickly and securely both in transit and at rest. It is the industry’s first FPGA device to offer integrated PCIe® Integrity and Data Encryption (IDE) support in hard IP6.

The combination of CXL 3.1 and LPDDR5X memory will help meet the growing demand for real-time processing and storage. Salil Raje, senior vice president of AMD's Adaptive and Embedded Computing Group, said the platform will help customers improve system throughput and utilization of memory resources to achieve higher performance.

IT Home briefly introduces the special terms that appear in this article:

Field Programmable Gate Array (FPGA)

An FPGA (field programmable gate array) is a semiconductor integrated circuit whose logic circuits can be programmed and configured by designers in the field.

FPGA allows users to program at the hardware level and change its function and structure as needed; FPGA usually has lower power consumption and is suitable for application scenarios with strict requirements on energy efficiency.

CXL 3.1

Compute Express Link (CXL) is an open standard, high-speed interconnect technology designed to provide efficient computing and storage solutions for modern data centers.

CXL 3.1 supports data transfer rates up to 64 GT/s, introduces the Trusted Security Protocol (TSP), and supports virtualization-based trusted execution environments (TEEs) to facilitate confidential computing workloads.

PCIe Gen 6

PCIe Gen 6 (PCI Express 6.0) is the latest released PCIe standard with a transfer rate of 64 GT/s, almost twice that of PCIe 5.0 (32 GT/s).

PCIe 6.0 introduces PAM-4 (Pulse Amplitude Modulation 4) technology, which further improves data transmission efficiency by transmitting more data bits in each signal cycle.

PCIe 6.0 is particularly suitable for areas such as data centers, artificial intelligence (AI), machine learning (ML), and high-performance computing (HPC).