Application of 1394 bus in TFT-LCD detection system based on ARM+FPGA

IEEE1394 is a high-speed serial bus originally proposed by Apple. In 1995, IEEE (Institute of Electrical and Electronics Engineers) recognized it as IEEE1394-1995 specification [1]. However, there are some ambiguous definitions in IEEE1394-1995 [2]. In order to solve these problems, IEEE1394a specification and IEEE1394b specification were proposed. As a mature bus, 1394 has the advantages of high transmission rate (transmission rate can reach 1.6 Gb/s, and can reach 3.2 Gb/s when using plastic optical fiber), hot plug and play, convenient topology, etc. It is widely used in military and aviation industries, and is even identified by NASA as a high-speed data bus for future spacecraft [9]. With the promotion and application of 1394 technology, it is a trend to apply it to industrial control systems. However, the application of 1394 bus in industrial systems in China is not yet in-depth. This paper mainly introduces the application of 1394 bus in TFT-LCD detection system, and proves the feasibility of the scheme through experiments.

1 Hardware structure of 1394 communication module

The main function of 1394 communication module is to collect image data of laser spot and to be responsible for communication between image acquisition board, Z-axis controller and PC. It includes 1394 chip (LLC and PHY), FPGA, ARM7 and 2 SRAMs.
The main function of ARM7 is to initialize 1394 chip, parse 1394 instructions forwarded by FPGA according to 1394 protocol, control data reception and transmission of 1394 link layer (LLC) chip, and indirectly control physical layer (PHY) chip through link layer chip. Almost all address lines, data lines and control signal lines are connected to FPGA, so FPGA plays a very important role in the whole 1394 communication module. Its main functions include: (1) configure ROM, initialize registers, set interrupt, self-identification and asynchronous data transmission through the "host interface" of 1394 LLC chip. (2) use "DM port" to transmit isochronous/asynchronous data. (3) control the reception and storage of data on 1394 bus. In order to facilitate the detection of the specific execution of instructions by the 1394 communication module, a serial port is extended on the 1394 communication module. By connecting it to the PC, the operation of the 1394 communication module can be monitored in real time through software on the PC, and instructions can also be sent through the software to control the 1394 communication module to perform corresponding actions.

The image data of the camera is sent to the 1394 bus through the 1394 physical port, processed by the 1394 link layer chip and the physical layer chip, and written into the extended SRAM through the ping-pong operation under the control of ARM7 and FPGA. In order to verify whether the collected image data is correct, the VGA interface is extended on the 1394 communication module. The FPGA reads the image data in the SRAM through the ping-pong method, and then outputs the data to the display through the VGA interface for intuitive display.

In order for the 1394 communication module to communicate normally with the PC, the PC must first be forced to be the root node on the 1394 bus. Therefore, after the 1394 communication module is connected to the 1394 network, it must detect whether the PC is the root node, otherwise it must be forced to reset until the PC is the root node. After the PC is the root node, data and instructions can be transmitted between the two. In addition, the Z-axis controller can receive motion control instructions from the PC or the 1394 communication module through the 1394 bus.
The ARM7 chip uses the LPC2292 of the enhanced LPC2200 series of NXP. The FPGA uses the EP1C6Q240C8 of the Cyclone series of Altera. The SRAM uses the IS61LV51216 of ISSI, which is used to cache the acquired image data for image processing or display in the later stage. The 1394 chip uses the TSB12LV32 (LLC) and TSB41AB3 (PHY) of TI. These two chips are compatible with the IEEE1394-1995 and IEEE1394a-2000 specifications, and integrate three physical ports that support a transmission rate of 400 MB/s. The TSB12LV32 provides an 8/16-bit selectable MCU interface and supports asynchronous transmission and isochronous transmission.


2 Software Design of 1394 Communication Module

The software design of 1394 communication module mainly includes the software design of ARM7-LPC2292 and FPGA-EP1C6Q240C8. According to different functions, the software design of ARM7 can be divided into ARM7 initialization, analysis of LLC chip instructions, read and write operations on FPGA, and serial port communication with PC. The software design of FPGA can be divided into read and write operations on LLC chip, communication with ARM7, control of VGA output, and operation on SRAM.

2.1 Initial Configuration of 1394

For the system to run normally, the initial configuration after power-on is very important. The functions of initial configuration are: (1) Correctly initialize the content of configuration ROM, which is the premise for PC to identify 1394 communication module and correctly install the corresponding driver. (2) If communicating with PC, set PC as root node. (3) Initialize the relevant registers of TSB12LV32. It mainly includes DM Control register (setting the status of DM port and some parameters), Interrupt (enabling all interrupts), Isochronous Port (status of isochronous transmission, setting the status of each physical port, transaction tag of isochronous data packet, etc.).

2.2 ARM7's response to TSB12LV32 interrupts

The important factor to ensure that ARM7 responds correctly to TSB12LV32 chip instructions is to accurately detect the interrupt signal of the TSB12LV32 chip and be able to read the interrupt register value of the CFR register, determine what kind of interrupt has occurred based on the specific value, clear the interrupt bit, and then decide the response based on the interrupt type. For example, after detecting the interrupt signal of TSB12LV32, read the interrupt register value with an offset address of 0x0C, and determine that bit9 is 1, that is, Data Mover packet received, indicating that a data packet has been received from the DM port. ARM7 only needs to clear the interrupt bit. However, not all interrupts only need to clear their interrupt bits without making other responses. For example: bit18, FIFO acknowledge interrupt, indicates that the data previously transmitted from ATF has been successfully received by the 1394 receiving node. At this time, in addition to clearing the interrupt bit, ARM7 also needs to read the value of the ACK code to confirm whether the 1394 receiving node has made a correct response.

2.3 LLC chip configuration ROM implementation

Configuration ROM formats have two formats: minimum format and normal format. All 1394 serial bus nodes that execute transactions should implement a configuration ROM, which provides the necessary information for configuring and diagnosing device-related problems. Some 1394 control chips (such as TSB43AA82A) can automatically respond to read requests for the configuration ROM. The programmer only needs to place the configuration ROM in a pre-set area. However, the LLC chip selected in this solution does not have this function, so it is necessary to manually respond to the read configuration ROM request sent by the host so that the configuration ROM can be correctly read into the host.

The 1394 communication module needs to act as a bus manager, loop controller, or isochronous resource manager, so it must have a configuration ROM in normal format. The main configuration items in the normal format of the configuration ROM include the root directory (Root Directory) and the bus information block (Bus_Info_Block). The root directory provides values ​​used to identify the driver and diagnostic software, and also provides optional pointers to other directories and data structures. The addresses pointed to by these pointers have the same structure as the root directory. The bus information block is used to specify bus-related functions [2]. The specific steps of setting the configuration ROM of ARM7 are as follows:

(1) Fill in the configuration ROM table according to the information provided, and calculate the check value according to the CRC check algorithm mentioned in the IEEE1394-1995 protocol.

(2) Parse the asynchronous read request data packet, analyze it as a read transaction, and the read target address is within the configuration ROM range, then fill the analyzed target address data into the read response data packet to respond to the read request.

After the host computer correctly reads the content of the configuration ROM, it will prompt that new hardware is found, and automatically install the corresponding driver for it after identifying the 1394 communication module.

2.4 Implementation of IEEE1394 isochronous data transmission

To realize isochronous data transmission, the following preparations need to be made: have two or more 1394 nodes, at least one of which is qualified to act as an isochronous resource manager, set the DM port mode of the node that is to send isochronous data to transmit mode, and set the DM port mode of the node that receives isochronous data to receive mode. Isochronous data transmission is divided into two types: automatic header insertion and manual header insertion; isochronous data reception is divided into two types: automatic header and tail removal and header and tail reception. In order to facilitate subsequent data processing, the isochronous mode of the isochronous data sending node is set to automatic header and tail insertion, and the isochronous mode of the isochronous data receiving node is set to automatic header and tail removal. The
isochronous data transmission process with automatic header insertion is as follows:

(1) A high pulse signal of DMREADY is received for one cycle.
(2) DMDONE is set to a low level.
(3) The DM port reads the header information automatically stored at address 38h and requests the link core to read the data to be sent to the 1394 bus.
(4) The link core obtains the header information stored in the header0 register.
(5) DMPRE generates a high pulse for one cycle.
(6) When DMRE is at a high level, it starts to obtain the data to be sent.
(7) When the link core reads the last data, the DM port starts to check whether the data has been sent to the channel defined by the control register. If the data has been sent to all channels, DMDONE is set to a high level after a small gap, and the isochronous transmission ends at this time; otherwise, the DM port continues to insert header information and transmit data until the data is sent to all channels.

The isochronous data receiving process that automatically removes the header and tail is as follows:

(1) If the sysc bit in the header is the same as the ISYNCRCVN information in the isochronous interface register (address 0x18h), DMPRE is set high for one cycle.
(2) After receiving the header, DMDONE is set high for one cycle. DMRW is set high when there is data passing later.
(3) After receiving all the data, DMRW is set low, and the DMD data line does not receive the tail.

3 Communication test

The communication experiment of the 1394 communication module is divided into two parts: testing the communication function specified by the 1394 protocol; verifying the correctness of the collected data. The experimental steps are as follows:

(1) Connect the 1394 communication module to the PC. After the module is powered on, first perform bus configuration, tree identification and self-identification. After the entire network is formed, the root node has been determined, and the addresses of each node have also been determined. When the 1394 bus performs the above actions, the content of the self-identification data packet is output through the extended serial port at the same time, including the number of nodes in the current network, the node number of the current node, whether it is the root node, and whether it has the function of isochronous resource management. At this point, the 1394 communication module has established a connection with the PC.
(2) Read the configuration ROM of the 1394 communication module through the PC to see if it can respond correctly.
(3) Perform asynchronous read and asynchronous write tests, which are divided into asynchronous read and write of bytes and asynchronous read and write of data blocks.
(4) Perform isochronous data transmission tests. See if the PC can receive the isochronous data packet sent by the 1394 communication module.
(5) Connect the camera, store the camera's image data in the SRAM of the 1394 communication module through isochronous transmission, and output it to the monitor through the VGA interface for display.

Except for step (5), the execution of each of the above steps will have results output on the serial port debugging assistant software. For example: after power-on, the 1394 communication module receives a self-identification packet and resets, and outputs "SID RCVD 2 Y 0 BUS RST.." on the debugging interface. "SID RCVD" means that the node has received a self-identification packet, "2 Y 0" means that there are two 1394 nodes in the current bus, the current node is the root node, and the node with isochronous resource management function is node 0. "BUS RST.." means that the node starts to reset the bus. The current node initiates an asynchronous read request to read the data at address 0x0400, and "ACK00010, 0x04049c44" will be displayed on the interface. "ACD00010" means that the other node has received the asynchronous read request command, and "0x04049c44" is the data stored at address 0x0400 returned. If two 1394 nodes want to perform isochronous data transmission, suppose the data sender is node 0 and the data receiver is node 1. Follow the steps below to test the isochronous data transmission between nodes: (1) Set the DM port mode of node 0 to send mode and the DM port mode of node 1 to receive mode. (2) Node 0 first reads the effective bandwidth on the bus. The upper interface receives "0x00000f33", which is the effective bandwidth of the current bus expressed in hexadecimal. Node 0 then applies for a certain bandwidth from the isochronous resource management node. The upper interface receives "ACK 00010", indicating that the bandwidth application is successful. (3) Read the effective channels on the bus and apply for the channel. The number of effective channels of the 1394 bus is stored in two registers, and the application is in order from low to high. Before applying for a channel, you must first confirm the number of channels currently used in the network, and then release the channel after the communication is completed. After issuing the command to read the effective channels, the upper interface receives "0xffffffff" and "0xffffffff", indicating that all channels on the bus are currently idle. You can apply for channel 1. After the application, the value of the low-order channel register becomes "0xfffffffe". After the previous three steps, the bandwidth and channel required for isochronous communication between node 0 and node 1 have been established. (4) Send an isochronous transmission instruction to see if node 1 has received the specified amount of isochronous data packets. The judgment is made through bit 9 (Data Mover packet receive) of the interrupt register.

This paper analyzes the application of 1394 bus based on FPGA+ARM in TFT-LCD detection system, which has a strong reference significance for the promotion of 1394 bus technology. The test experiment shows that the 1394 bus allocates a fixed bandwidth when performing isochronous communication, ensuring the fast and accurate transmission of image data. At the same time, the various modules of the entire detection system are connected through the 1394 bus, which can be completely separated from the PC and run independently. Asynchronous transmission is used to transmit control instructions, which is both convenient and stable.