Design of Virtual FPGA Logic Verification Analyzer

Design of Virtual FPGA Logic Verification Analyzer

With the widespread use of FPGA technology, there is an increasing need for an instrument that can test and verify whether the logic timing of the circuit downloaded into the FPGA chip is correct. At present, although high-end logic analyzers produced by large companies such as Agilent and Tektronix can realize the test and verification function of FPGA circuits, such instruments are expensive, generally costing hundreds of thousands of RMB. Therefore, it is very valuable to research and develop an instrument with a moderate price and the test and verification functions of logic analyzers and FPGA circuits.

The logic verification analyzer based on virtual instrument technology introduced in this paper adopts FPGA technology to realize the main design of the instrument hardware part, and uses the graphical programming language LabVIEW to realize the test software design of the instrument. This paper explains the overall design scheme and working principle of the virtual FPGA logic verification analyzer, and gives a specific introduction to the development and design of the two main working links of the instrument. In addition to the basic test and verification functions of FPGA circuits, the virtual FPGA logic verification analyzer also has the functions of logic analyzer and generating stimulus signals. It is an ideal instrument for microcomputer system and digital circuit design, debugging, software development and simulation.

Design of Virtual FPGA Logic Verification Analyzer

1 Overall Design of Virtual FPGA Logic Verification Analyzer

The virtual FPGA logic verification analyzer uses the computer as the data display control, and the display, mouse and keyboard as the user panel of the instrument. Its composition block diagram is shown in Figure 1.

Figure 1 Block diagram of the virtual FPGA logic verification analyzer

The basic working principle of this instrument is: the computer edits the simulated excitation signal of the input circuit to the designed circuit under test, collects and stores it at the same time, and then transmits it back to the computer, and finally performs logic timing analysis of the circuit, so as to realize the basic test and verification function of the instrument's FPGA circuit, as well as the function of logic analyzer and the function of generating excitation signals. The working steps of the instrument are shown in Figure 2.

Figure 2 Virtual FPGA logic verification analyzer workflow diagram

2 Hardware Design of Virtual FPGA Logic Verification Analyzer

The hardware components of the virtual FPGA logic verification analyzer include three parts:

① Mainboard, which has multiple functions such as data acquisition, data storage, timing counting, data communication between the mainboard and the computer. Since FPGA (field programmable gate array) can be programmed repeatedly for unlimited times, it is fast, convenient and practical, and has the characteristics of on-site simulation debugging and verification, the more complex controller part and sampling part of this system are all implemented by FPGA; the others are composed of peripheral chips. The peripheral chips mainly have data channel parts such as RAM and data buffer and latch.
② FPGA circuit board under test.
③ General personal computer with the ability to run graphical programming software.

3 Software Design of Virtual FPGA Logic Verification Analyzer

The software design of the virtual logic verification analyzer uses NI's graphical programming language tool LabVIEW7.0. The FPGA test verification software is a high-performance software that includes digital waveform opening, editing, saving, and browsing. With the cooperation of hardware, it can complete the download of digital waveforms, that is, load the edited and generated waveforms in the form of data to the stimulus port of the FPGA circuit board under test, and retrieve the test data from the output port for display to verify whether the programmable logic design downloaded by the user to the FPGA circuit board under test is correct. The main interface of the software is shown in Figure 3.

Figure 3 Main interface of the software

Introducing the two working steps of the virtual FPGA logic verification analyzer

1 Edit stimulus signal

The excitation signal source of the virtual FPGA logic verification analyzer is implemented using pure software LabVIEW. The excitation signal source can choose to open, edit or save the digital excitation waveform in the form of a truth table (bit-wise) or a coding table (bus-wise), and the number of cycles can be selected. Its main technical indicators are as follows.

① Input mode: truth table, bus mode editing input;
② Output channel: 13 output excitation signal data channels;
③ Display mode:
A: timing waveform display, horizontal displacement and horizontal expansion;
B: data display, divided into binary and hexadecimal display.

2. Measure the circuit board under test

In the workflow of the virtual FPGA logic verification analyzer, the work of measuring the circuit board under test is to input the edited simulation stimulus signal to the designed circuit board under test, and collect and store the data of the tested circuit board at the same time. The collection work in this step is mainly implemented by FPGA, and the storage work is completed by RAM. Through analysis and demonstration, this design uses the Cyclone series chip of ALTER Company, model EP1C6Q144. It uses a 1.5V core voltage, an embedded 92160-bit storage interval, and can provide two phase-locked loops and dual-signal data transmission rate (DDR) interface circuits. In the design, the main technical indicators of the logic analyzer circuit and the acquisition circuit are as follows.

①Acquisition clock: external clock and internal clock;
②Internal clock frequency: 25kHz, 50kHz, 100kHz, 250kHz, 500kHz, 1MHz, 5MHz, 10MHz;
③Acquisition storage points: 1~2048;
④Trigger mode: clock trigger, external trigger, word trigger and key trigger.
 
Conclusion

The virtual FPGA logic verification analyzer introduced in this article uses FPGA technology to implement the main design of the instrument hardware part, and uses the graphical programming language LabVIEW to implement the instrument test software design. Facts have proved that the virtual FPGA logic verification analyzer designed by this scheme not only has the basic test and verification functions of FPGA circuits, but also has the functions of logic analyzer and generating stimulus signals. Through practical proof, the instrument has the characteristics of powerful functions, good stability, strong scalability, convenient and flexible operation, and is a good auxiliary instrument for teaching, experiments and scientific research.