Location:Training / Embedded Development / FPGA / The first issue of FPGA design of ZYNQ video, the leader of punctual atoms / Practical operation: Create timing constraint file

Lecture 1 Introduction to ZYNQ Lecture
2 Introduction to development board resources
Lecture 3 Installation of Vivado software Lecture
4 Use of Vivado software Lecture
5 Hardware debugging of Vivado software
Lecture 6 Use of Vivado Simulator simulation software
Lecture 7 Creating timing constraint files
Lecture 8 Installation of ModelSim software Lecture
9 Use of ModelSim software Lecture
10 LED light flashing experiment
Lecture 11 Button control LED light experiment
Lecture 12 Button control buzzer experiment
Lecture 13 Touch button control LED light experiment Lecture
14 Breathing light experiment
Lecture 15 Clock IP core experiment
Lecture 16 RAM IP core experiment
Lecture 17 FIFO IP core experiment Lecture
18 UART serial communication
Lecture 19 RS485 communication experiment
Lecture 20 RGB LCD color bar display experiment Lecture
21 LCD characters and picture display experiment
Lecture 22 HDMI color bar display experiment
Lecture 23 HDMI square mobile display experiment
Lecture 24 EEPROM read and write test experiment Lecture
25 RTC clock experiment Lecture
26 Frequency meter experiment
Lecture 27 High-speed ADDA experiment
Lecture 28 IO Expansion board experiment
Lecture 29 MDIO interface read and write test experiment
Lecture 30 Ethernet ARP test experiment
Lecture 31 Ethernet UDP test experiment
Lecture 32 Ethernet video transmission experiment based on OV7725
Lecture 33 Ethernet video transmission experiment based on OV5640