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21.Core initialization svc mode
21.Core initialization svc mode To set the system to work in svc privileged mode, we need to set the CPSR program status register from the previous study. In the ARM Architecture Reference Manual pdf document, 2 Program Status Register ...
Keywords: Core initialization svc mode privileged mode
Publish Time:2024-10-30
22.Core initialization watchdog
22.Core initialization watchdog Watchdog timer, in the embedded field, some devices need to work in some extreme environments, that is, places where people rarely or hard to reach. In the long-term operation, it is inevitable that there will be malfunctions and crashes. ...
Keywords: Core initialization watchdog
Publish Time:2024-10-30
23.Core initialization interrupt shielding-2440
23.Core initialization interrupt shielding-2440 In the previous section, when I set up to disable the watchdog, I had already set WTCON[2] to 0, thus disabling the interrupt. As shown in the following figure: This section is to disable the interrupt register: The following is the 2440 chip processing ...
Keywords: Core initialization interrupt mask 2440
Publish Time:2024-10-29
24.Core initialization interrupt shielding-6410
24.Core initialization interrupt shielding-6410 Open the 6410 chip manual and find the vector interrupt control register in 12 VECTORED INTERRUPT CONTROLLERS. Vector interrupts (6410, 210) are often completed by hardware. ...
Keywords: Core initialization interrupt mask 6410
Publish Time:2024-10-29
25.Core initialization interrupt shielding-210
25.Core initialization interrupt shielding-210 The mechanism for masking interrupts in the 210 is the same as that in the 6410. Moreover, both are vectored interrupts, and many interrupts are implemented in hardware, unlike the 2440. However, there are 4 interrupt mask registers in the 210: ...
Keywords: Core initialization interrupt mask 210
Publish Time:2024-10-29
26.Core initialization: turn off MMU and cache
26.Core initialization: turn off MMU and cache Let's look at the ARM memory hierarchy: you can see that the fastest are the processor and internal registers, which are few in number and very expensive. Next is the TCM tightly coupled memory: cache and main memory ...
Keywords: Core initialization turn off MMU cache
Publish Time:2024-10-29
27. Operation of lighting up LED
27. Operation of lighting up LED Led can be used as a tool for debugging programs: In the early stages of development of embedded system software, such as Bootloader and kernel, since hardware such as serial ports have not yet been initialized, debugging methods are quite useful. ...
Keywords: Light up LED debug program Bootloader
Publish Time:2024-10-29
28. Clock initialization
28. Clock initialization ARM system clock initialization: This requires knowing what is a clock pulse signal, what is a clock frequency, and what is a clock source. Clock pulse signal: Clock pulse signal: a certain voltage amplitude, a ...
Keywords: Clock Initialization ARM system
Publish Time:2024-10-29
29. Basics of memory
29. Basics of memory Classification of memory: Memory has become an indispensable component in PC or embedded hardware platform due to its advantages such as fast access speed and simple access method. Before you start learning how to use memory, ...
Keywords: memory basics access speed
Publish Time:2024-10-29
30.2440 Knowledge of Memory
30.2440 Knowledge of Memory First, let's look at the address lines of 2440: mini2440 schematic pdf The 2440 chip provides 27 address lines = 128M. The S3c2440 chip provides only 27 address lines addr[0:26] on the pins provided to the outside. ...
Keywords: 2440 memory address line
Publish Time:2024-10-29
31.6410 Knowledge of Memory
31.6410 Knowledge of Memory 6410 address space distribution: S3C6410 processor has a 32-bit address bus, and its address space is. The upper part is reserved for peripherals, and the lower 2GB area can be divided into two parts: main storage area and peripheral area. ...
Keywords: 6410 memory address bus
Publish Time:2024-10-29
35. Knowledge of BSS segment
35. Knowledge of BSS segment In C language, initialized global variables are stored in the data segment, initialized local variables are stored in the stack, space allocated by malloc is stored in the heap, and uninitialized global variables are stored in the b ...
Keywords: BSS segment C language data segment
Publish Time:2024-10-29
36. From assembly to C (bl1 to bl2)
36. From assembly to C (bl1 to bl2) An absolute jump must be used to jump from assembly to C: Project code: Add main in Makefile o:Start S:Make Compile: Main C code: define GPKCON (volatile unsigned ...
Keywords: Assembly C absolute jump
Publish Time:2024-10-29
37. Mixed programming of C and assembly
37. Mixed programming of C and assembly Create a new light c: modify start S: modify Makefile: add light o Finally, make succeeds and the burning is successful. Similarly, we can also call the function in our assembly in the C function: modify star ...
Keywords: C assembly mixed programming
Publish Time:2024-10-29
10. Code Migration
10. Code Migration ...
Keywords: Code migration ARM
Publish Time:2024-10-29
1. Brief explanation of ARM registers
1. Brief explanation of ARM registers 1 ARM register brief explanation From the ARM Architecture Reference Manual pdf, we can get information: 31 general registers, 6 status registers (one cpsr, 5 spsr). ...
Keywords: ARM Register Status Register
Publish Time:2024-10-22
2. Simple implementation of assembly code
2. Simple implementation of assembly code The reason for using assembly is very simple, that is, the efficiency of assembly code. When the machine starts, the efficiency of assembly is used to initialize the hardware and provide conditions for loading the kernel. ...
Keywords: Assembly code assembly ARM
Publish Time:2024-10-22
3. Arm machine code
3. Arm machine code First, the assembly program is converted into machine code before it can be run in the machine. First, we disassemble the elf file generated in the bare metal code above: start elf: file format elf32-li ...
Keywords: Arm machine code assembler
Publish Time:2024-10-22
4. Coprocessor access instructions
4. Coprocessor access instructions Coprocessors are used to perform specific processing tasks. For example, a coprocessor for mathematical calculations can control digital processing to reduce the burden on the processor. ARM can support up to 16 coprocessors, including CP1 ...
Keywords: Coprocessor access instructions process tasks
Publish Time:2024-10-22
6. Learning the exception vector table --- setting the SVC mode
6. Learning the exception vector table --- setting the SVC mode This is the manual information. We can see that to set the svc mode, we just need to set the last five bits of our cpsr to 0b10011. Cpsr structure: Next, we will set the last five bits of cpsr to ...
Keywords: Exception vector table SVC mode bic instruction
Publish Time:2024-10-22

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