MSP430 clock setting and application

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MSP430 clock setting and application [Copy link]

In the MSP430 microcontroller, one clock cycle = the inverse of the MCLK crystal oscillator. If the MCLK is 8MHz, then one clock cycle is 1/8us.

One machine cycle = one clock cycle, that is, each action of 430 can complete a basic operation.

One instruction cycle = 1~6 machine cycles, depending on the specific instruction.

In addition, instruction length is just a storage unit and has no necessary relationship with time.

The clock module of the MSP430 microcontroller mainly includes:

Three clocks: auxiliary clock ACLK, main clock MCLK, subsystem clock SMCLK

Three oscillators: low frequency clock source LFXT1, high frequency clock source XT2, digitally controlled RC oscillator DCO

The clock required for the operation of the MSP430 microcontroller is generated by the oscillation of these oscillators and then processed.

(1)ACLK: obtained by dividing the LFXT1CLK signal by 1/2/4/8, mainly used as a low-speed peripheral clock

(2) MCLK: It is determined by one of LFXT1CLK, XT2CLK, and DCOCLK. It is selected by software and then divided by 1/2/4/8. It is mainly used for CPU and system

(3) SMCLK: It can be determined by LFXT1CLK and DCOCLK, or XT2CLK and DCOCLK, and then obtained by 1/2/4/8 division. It is mainly used for high-speed peripheral modules.

The clock module of MSP430 is determined by five registers: DCOCTL, BCSCTL1, BCSCTL2, IE1, and IFG1. The specific functions are as follows:

DCOCTL: Control DCO oscillator

BCSCTL1: controls XT2, LFXT1, DCO oscillation, and controls the frequency division of ACLK

BCSCTL2: Set the oscillator for each of the three clock sources

We set the registers in the program, that is, we set the three oscillators. After the clock oscillator is set, we also need to set the clock module, that is, let the three clock modules MCLK SMCLK ACLK select the corresponding clock oscillator to get clocks of different frequencies.

After the PUC signal, the system selects the internal resistor to achieve the frequency output. RSELx = 4 and DCOx = 3, which makes the DCO have a moderate frequency at the beginning. The clock signals of MCLK and SMCLK all come from DCO, which is about 800KHz (chip manual). After the PUC signal, LFXT1 is set to LF mode (XTS=0), and the HF mode (XTS=1) and the XT2 oscillator are turned off.

(1) DCOCTL: DCO control register, address is 56H, initial value is 60H

// 7 6 5 4 3 2 1 0

// DCO2 DCO1 DCO0 MOD4 MOD3 MOD2 MOD1 MOD0

//

// DCO0~DCO2: DCO Select Bit, defines one of 8 frequencies, and the frequency is defined by the current injected into the DC generator

// MOD0~MOD4: Modulation Bit, frequency fine-tuning

//

//DCO settings: Set the DCO frequency by setting DCOCTL and BCSCTL1

// (1)DCO adjustment:

Set the DCOR bit to select external or internal resistors to determine a reference frequency

Use RSELx of BCSCTL1 register to divide the clock frequency and determine the clock frequency.

Select the frequency by adjusting DCOx in the DCOCTL register in sections based on the nominal frequency;

Fine-tune the frequency by using the value of MODx in the DCOCTL register to select a frequency between DCOx and DCOx+1

// Note: When DCO operates at the highest frequency, the normal value of the internal resistance is about 200k, and the operating frequency of DCO is about 5MHz.

example:

//The initial value of DCOCTL is 60H, that is, DCOCTL |= DCO1 + DCO2;

DCOCTL |= DCO0 + DCO1 + DCO2; // Max DCO

//MOD0~MOD4: Modulation Bit, frequency fine-tuning generally keeps the default

//By default, RSELx=4

(2) BCSCTL1 (ACLK): Basic Clock System Control 1, address is 58H, initial value is 84H

// 7 6 5 4 3 2 1 0

// XT2OFF XTS DIVA1 DIVA0 XT5V RSEL2 RSEL1 RSEL0

//

// RSEL2~RSEL0: Select an internal resistor to determine the nominal frequency (0 is the lowest, 7 is the highest)

// XT5V: 1, this bit is not used, reset must be selected

// DIVA0~DIVA1: Select the frequency division coefficient of ACLK. DIVA=0,1,2,3 (DIVA_0,DIVA_1...), the frequency division coefficients of ACLK are: 1,2,4,8

// XTS: Select whether LFXT1 works in low frequency crystal mode (XTS=0) or high frequency crystal mode (XTS=1)

// XT2OFF: Controls the opening (XT2OFF=0) and closing (XT2OFF=1) of the XT2 oscillator

//

// BCSCTL1 setting: initial value is 84H

//Use XT2 oscillator

//Control the opening (XT2OFF=0) and closing (XT2OFF=1) of the XT2 oscillator

BCSCTL1 &= ~XT2OFF;//Clear OSCOFF/XT2

do

{

IFG1 &= ~OFIFG; // Clear OFIFG

OSC_Delay = 255;

while(OSC_Delay --); //Delay waiting

}

while(IFG1 & OFIFG); //Until OFIFG=0

//RSEL2~RSEL0: Select an internal resistor to determine the nominal frequency (0 is the lowest, 7 is the highest)

BCSCTL1 |= RSEL0 + RSEL1 + RSEL2;//XT2on,max RSEL

//Select the frequency division coefficient of ACLK: DIVA=0,1,2,3, the frequency division coefficients of ACLK are: 1,2,4,8

//BCSCTL1 |= DIVA_2; //divide ACLK by 2

//(3)BCSCTL2(SMCLK,MCLK):Basic Clock System Control 2, address is 58H, initial value is 00H

// 7 6 5 4 3 2 1 0

// SELM1 SELM0 DIVM1 DIVM0 SELS DIVS1 DIVS0 DCOR

//

// DCOR: Enable External Resister, 0—Select internal resistor, 1—Select external resistor

// DIVS0~DIVS1: DIVS=0,1,2,3, corresponding to SMCLK division factors of 1,2,4,8

// SELS: Select the clock source of SMCLK, 0: DCOCLK, 1: XT2CLK/LFXTCLK

// DIVM0~DIVM1: select the frequency division factor of MCLK, DIVM=0,1,2,3, the corresponding frequency division factor of MCLK is 1,2,4,8

// SELM0~SELM1: Select the clock source of MCLK, 0, 1: DCOCLK, 2: XT2CLK, 3: LFXT1CLK

//

// BCSCTL2 setting: initial value is 00H

//Set BCSCTL2, select the clock source XT2 for MCLK and SMCLK, and set its division factor

//Note: ACLK can only come from LFXT1, and the frequency division of ACLK can be set in BCSCTL1, which means that the maximum value of ACLK can only be 32768Hz (XIN and XOUT are indirectly connected to a 32.768KHz crystal oscillator)

//DCOR is generally set to the default value

//Set the division factor of SMCLK, DIVS0~DIVS1: DIVS=0,1,2,3, corresponding to the division factor of SMCLK is 1,2,4,8

//BCSCTL2 = DIVS_0;

//BCSCTL2 = DIVS_1;

//BCSCTL2 = DIVS_2;

//BCSCTL2 = DIVS_3;

//Set the frequency division factor of MCLK, DIVM0~DIVM1: DIVM=0,1,2,3, corresponding to the frequency division factor of MCLK is 1,2,4,8

//BCSCTL2 = DIVM_0;

//BCSCTL2 = DIVM_1;

//BCSCTL2 = DIVM_2;

//BCSCTL2 = DIVM_3;

//BCSCTL2: Set the oscillators for the three clock sources

//SELM0~SELM1: Select the clock source of MCLK, 0, 1: DCOCLK, 2: XT2CLK, 3: LFXT1CLK

//Select MCLK clock source as XT2,

//BCSCTL2 = SELM_2;

//SELS: Select the clock source of SMCLK, 0: DCOCLK, 1: XT2CLK/LFXTCLK

//Select SMCLK clock source as XT2

//BCSCTL2 = SELS;

//Select MCLK and SMCLK as XT2

BCSCTL2 = SELM_2 + SELS;

//(4)IE1,Interrupt Enable Register 1

// 7 6 5 4 3 2 1 0

// OFIE

// 7~2 and 0 : These bits may be used by other modules

// OFIE:Oscillator fault interrupt enable. 0---Interrupt not enabled

// 1---Interrupt enabled

//(5)IEG1,Interrupt Flag Register 1

// 7 6 5 4 3 2 1 0

// OFIFG

// 7~2 and 0 : These bits may be used by other modules

// OFIE:Oscillator fault interrupt flag. 0 No interrupt pending

// 1 Interrupt pending

//

After the PUC signal, by default, DCOCLK is used as the clock signal of MCLK and SMCLK. Since the initial value of DCOCTL is 60H, the clock source of MCLK can be set to LFXT1 or XT2 as needed. The setting sequence is as follows:

//(1) Clear OSCOFF/XT2

//(2) Clear OFIFG

//(3) Delay waiting for at least 50us

//(4) Check OFIFG again. If it is still set, repeat steps (1) to (4) until OFIFG = 0.

//(5) Set the corresponding SELM of BCSCTL2