S5PV210 Development -- How much do you know about SPI?

1. Introduction to SPI

See: SPI Detailed Explanation

SPI (serial peripheral interface) bus technology is a synchronous serial interface introduced by Motorola. It is used for full-duplex, synchronous serial communication between CPU and various peripheral devices. It only needs four lines to complete the communication between MCU and various peripheral devices. These four lines are: serial clock line (CSK), host input->slave output data line (MISO), host output<-slave input data line (MOSI), and low-level effective slave select line CS. When SPI is working, the data in the shift register is output from the output pin (MOSI) bit by bit (high bit first), and the data received from the input pin (MISO) is shifted to the shift register bit by bit (high bit first). After sending a byte, the byte data received from another peripheral device enters the shift register. That is, the essence of completing a byte of data transmission is the exchange of the contents of the registers of two devices. The clock signal (SCK) of the master SPI synchronizes the transmission.

2. SPI master and slave hardware connection diagram

See: SPI - Wikipedia

SPI is used to communicate with various peripherals, such as:

Sensors: temperature, pressure, ADC, touch screen, video game controllers

Control devices: audio codecs, digital potentiometers, DACs

Camera lens: Canon EF lens mount

Communications: Ethernet, USB, USART, CAN, IEEE 802.15.4, IEEE 802.11, handheld video games

Memory: Flash and EEPROM

Real Time Clock

LCD, sometimes even used to manage image data

Any MMC or SD card (including SDIO variants[6] )

For high-performance systems, FPGAs sometimes use the SPI interface as a slave to a host, as a master sensor, or for use with SRAM flash memory for booting if they are based on it.

Check the chip manual and schematic diagram. DM368 has 5 groups of SPI buses, each with 3 chip selects; Hi3516A has 2 groups of SPI buses, each with 3 chip selects.

SPI bus one master to multiple slaves connection method:

Typical SPI bus: master and three independent slaves

In an independent slave configuration, there is a separate chip select line for each slave. Pull-up resistors between the power and chip select lines are strongly recommended for each independent device to reduce crosstalk between devices. [3] This is the way SPI is commonly used. Because the MISO pins of the slaves are connected together, they need to be tri-stated pins (high, low, or high impedance).

Daisy-chained SPI bus: master and coordinated slaves

Some products implementing SPI can be connected in a daisy-chain configuration, with the first slave output connected to the second slave input and so on. Each slave's SPI port is designed to emit during the second set of clock pulses an exact copy of the data it received during the first set of clock pulses. The entire chain acts as a communicating shift register; daisy chaining is typically accomplished with a bank of shift registers provided by the SPI input or output. This feature requires only a single SS line from the master, rather than a separate SS line for each slave. Other applications that can potentially interoperate with SPI that require a daisy-chain configuration include SGPIO, JTAG,[5] and two-wire interfaces.

3. Four working modes of SPI

(1) Working mode

SPI has four working modes. The difference between each working mode lies in the different SCLK. The specific operation is determined by CPOL and CPHA.

CPOL: (Clock Polarity), clock polarity:

When CPOL is 0, the level is low when the clock is idle;

When CPOL is 1, the level is high when the clock is idle;

CPHA: (Clock Phase), clock phase:

When CPHA is 0, data is collected on the rising edge of the clock cycle and output on the falling edge of the clock cycle;

When CPHA is 1, data is collected on the falling edge of the clock cycle and output on the rising edge of the clock cycle;

CPOL and CPHA can be 0 or 1 respectively, corresponding to four combinations.

The timings of the four working modes are:

(2) Identification skills

It is mentioned above that there are four working modes. How can you confirm which working mode your device is using?

Take the GV7601SDI decoding chip as an example:

See: GV7601 SDI decoding chip DATASHEET

See: Hi3516A Development--GV7601 Hardware Design

1. First confirm the SCLK polarity required by the slave, whether it is at low potential or high potential when not working, and thus confirm that CPOL is 0 or 1

The clock level is low when it is idle, so CPOL is 0.

2. Use the timing diagram in the slave chip datasheet to confirm whether the slave chip collects data on the falling edge of SCLK or on the rising edge of SCLK.

translate:

During a read sequence (command word R/W bit set high), serial data is transmitted or received MSB first, synchronously with the rising edge of the serial clock SCLK. The chip select (CS) signal must be set low at least 1.5ns (t0 in Figure 4-62) before the first clock edge to ensure correct operation. The first bit (MSB) of the serial output (SDOUT) is available after the last falling SCLK edge of the read command (t5 in Figure 4-63) word, and the remaining bits are output on the negative edge of SCLK.

NOTE: When multiple devices are connected to the GSPI chain, only one CS can be asserted during a read sequence.

During a write sequence (command word R/W bit set low), a wait state of 37.1ns (t4 in Figure 4-62) is required between the command word and the following data word. This wait state must also be maintained between consecutive command words/data words during a write sequence. When the auto-increment mode is selected (AutoInc = 1), wait states must be maintained between consecutive data words following the initial command word/data word sequence. During a write sequence, all command and subsequent data words input to the SDIN pin are output at the SDOUT pin unchanged. When several devices are connected to a GSPI chain, data can be written to all devices simultaneously with CS low.

Result: CPHA is 0

4. Advantages and Disadvantages

Advantages[edit]

In the default version of this protocol communication is full-duplex.

Push-pull drivers (rather than open-drain) provide good signal integrity and high speed

Higher throughput than I²C or SMBus. Not limited to any maximum clock speed, thus enabling potentially high-speed

Full protocol flexibility for transmitted bits

Not limited to 8-bit words

Choose the size, content and purpose of the email

Extremely simple hardware interface

Typically lower power requirements than I²C or SMBus due to less circuitry (including pull-up resistors)

No arbitration or related failure modes

Slave devices use the master clock and do not require a precision oscillator

The slave does not need a unique address - unlike I²C or GPIB or SCSI

No transceiver required

Uses only 4 pins on the IC package, and wires in the board layout or connector, much less than parallel interfaces

At most one unique bus signal (chip select) per device; all others shared

Signal unidirectional allows simple electrical isolation

Simple software implementation

Disadvantages

Requires larger pins in the IC package than I²C, even in the three-wire variant

No band addressing; external band chip select signals need to be on the shared bus

No hardware flow control by the slave (but the master can delay the next clock edge to slow down the transfer rate)

No hardware slave acknowledgement (master can transmit anywhere and not know it)

Usually only one master device is supported (depending on the device's hardware implementation)

No error checking protocol is defined

Without a formal standard, verifying conformance is impossible

Compared to RS-232, RS-485, or CAN bus, which only handles short distances. (The distance can be extended using transceivers, etc. for RS-422)

Many existing changes make it difficult to find development tools such as host adapters that support these changes

SPI does not support hot-swapping (dynamic addition of nodes).

Interrupts must be implemented either with out-of-band signaling, or can be faked by using periodic polling similar to USB 1.1 and 2.0

Some variants like Multi-I/O SPI and the three-wire serial bus defined below are half-duplex.

5. SPI communication on MCU

See: MCU software simulation SPI interface - deepen understanding of SPI bus protocol

See: Coding SPI software

See: SOFTWARE SPI EXAMPLES FOR THE C8051F30X FAMILY

//-----------------------------------------------------------------------------

//SPI_defs.h

//-----------------------------------------------------------------------------

// Copyright 2001 Cygnal Integrated Products, Inc.

//

//AUTH: BD

// DATE: 7 DEC 01

//

// This file defines the pins used for the SPI device.

// The SPI device is mapped to pins P0.0 - P0.3, but can be modified to map to

// any of the available GPIO pins on the device.

//

#ifndef SPI_DEFS

#define SPI_DEFS

sbit MOSI = P0^0; // Master Out / Slave In (output)

sbit MISO = P0^1; // Master In / Slave Out (input)

sbit SCK = P0^2; // Serial Clock (output)

sbit NSS = P0^3; // Slave Select (output to chip select)

#endif

Working mode: (0, 0)

//-----------------------------------------------------------------------------

// SPI_MODE0.c

//-----------------------------------------------------------------------------

// Copyright 2001 Cygnal Integrated Products, Inc.

//

//AUTH: BD

// DATE: 14 DEC 01

//

// This file contains a 'C' Implementation of a Mode 0 Master SPI device.

//

// Target: C8051F30x

// Tool chain: KEIL C51 6.03 / KEIL EVAL C51

//

//

#include // SFR declarations

#include "SPI_defs.h" // SPI port definitions

//-----------------------------------------------------------------------------

// SPI_Transfer

//-----------------------------------------------------------------------------

//

// Simultaneously transmits and receives one byte using

// the SPI protocol. SCK is idle-low, and bits are latched on SCK rising.

//

// Timing for this routine is as follows:

//

// Parameter Clock Cycles

// MOSI valid to SCK rising edge 6

// SCK rising to MISO latched 2

// SCK falling to MOSI valid 7

// SCK high time 8