Design and simulation of quad-redundant communication board based on CAN core

With the continuous development of electronic technology, computer application technology and EDA technology, the development of digital systems using FPGA has been widely used in the fields of communication, aerospace, medical electronics, industrial control, etc. FPGA has become one of the preferred methods for hardware design today. PC/104 is an industrial control bus specially defined for embedded control. It has been widely used for its unique stack structure and low power. As a mainstream field bus, the industrial control local area network CAN (Controller Area Network) bus has strong anti-interference ability, is easy to network, and has a very broad application prospect. The unique combination of PC/104 bus and CAN bus further broadens the application field of CAN bus.

1 FPGA-based CAN core design

This design uses Altera's Cyclone III series FPGA EP3C25, and the development platform uses Altera's Quartus II software. The design of the CAN core is based on the SJA1000 functional structure.

The functional block diagram of the CAN core is shown in Figure 1. The CAN bus controller IP core follows the CANbus 2.0 standard, and its functions and register operations are compatible with SJA1000. The IP core is coded in VHDL and adopts fault-tolerant design, which can suppress the data bit flipping of storage devices and greatly improve the reliability of the IP core. The CAN core can be implemented in FPGA or ASIC. It contains 3 main modules: register group (can_registers), bit timing logic (can_btl), and bit stream processor (can_bsp).

Register group (CAN Register): The external microprocessor can directly access these registers through the address. When sending data, the microprocessor writes the data to be sent into the transmit buffer and sets the transmit request bit of the command register to start sending. After receiving the data, the core controller stores it in the receive buffer and notifies the bit controller to take it away. At the same time, there is a 64-byte receive FIFO in the CAN register, which can store at least 2 data frames at a time.

Bit timing logic (BTL): used to monitor the CAN bus and process the bit timing related to the CAN bus. At the beginning of the message, when the bit timing logic detects a transition from a recessive bit to a dominant bit on the bus, it will synchronize its internal logic to the bit stream, which is called hard synchronization; subsequently, in the process of receiving the message, when a transition from a recessive bit to a dominant bit is detected, it will resynchronize to the bit stream, which is called soft synchronization. The bit timing logic also determines the position of each bit cycle sampling point according to the values ​​of bus timing register 0 and bus timing register 1 to compensate for the errors caused by transmission delay and phase drift; at the same time, the corresponding sampling mode (single sampling or 3 times) is adopted according to the setting of bus timing register 1 to sample the data on the bus.

Bit stream processor (BSP): According to the functions it implements, it is divided into three modules: data receiving module, data sending module and error handling module. The data receiving module removes the bit padding from the sampled data sent from the bit timing logic and sends it to the shift register for serial-to-parallel conversion, then performs CRC check on the parallel data, and sends a response signal when the message is received, indicating that the reception is correct. Finally, the feature code of the received message is compared with the content of the acceptance mask register to decide whether to write the received message into the receiving FIFO. The data receiving module frames the data to be sent and performs CRC calculation, then sends it to the shift register for parallel-to-serial conversion, and then encodes the serial data (bit padding) and sends it to the bus. The error monitoring module detects system errors according to the error monitoring mechanism described in the protocol specification, sets the corresponding register, and notifies the device controller. The module adds, subtracts or clears the counters when appropriate according to the 12 error monitoring rules described in the protocol. The controller determines its fault state based on the values ​​of the two counters and the value of the error limit register: Error Active, Error Passire or Bus Off On.

2 Hardware Circuit Design

According to the overall design of the system, because the maximum operating frequency of the existing CAN bus transceiver is 1 MHz, after increasing the communication speed of CAN, the existing CAN bus transceiver cannot meet the needs, so the RS485 transceiver is used instead. Since the RS485 transceiver is differential transmission, it cannot complete the self-transmitting and self-receiving functions of the communication card, so an external CAN Hub is required. In addition, to perform optical fiber transmission and complete the optical logical bus structure, an external Hub is also required. Therefore, this hardware design is divided into two parts: the design of the CAN communication board and the design of the CAN Hub.

(1) CAN communication board hardware circuit design

The core device of the CAN communication board is FPGA, which simultaneously completes "dual-optical and dual-electrical" communication. The structure of the hardware communication board is shown in Figure 2.

As a module of PC/104 system, it needs to be connected to PC/104 bus, so the bus standards specified by PC/104 standard must be consistent in data, address and control bus.

This design needs to be quad-redundant, and 4 CAN cores need to be added in the design. The FPGA EP3C25 of Altera's Cyclone II series is selected.

Since the working voltage of PC/104 is 5 V and the working voltage of FPGA is 3.3 V, a level converter 74LVC245 needs to be added between PC/104 and FPGA to protect FPGA.

(2) Optical transceiver circuit The

high-speed optical transmitter of this system adopts HFBR-1414 low-power high-speed optical transmitter device, and its optical emission wavelength is 820 nm. This transmitter can be used with the following 4 types of optical fibers: 50/125 μm, 62.5/125 μm, 100/140 μm, 200 μm (HCS). HFBR-1414 uses a dual-lens optical system with high light emission efficiency. When the driving current is 60 mA, an optical power of -15 dBm can be obtained on a 50/125 μm optical fiber. The optical receiver uses HFBR-2412, which integrates a photodiode, a DC circuit, and an open-collector Schottky transistor. The HFBR-2412 optical receiver can be used with the optical transmitter HFBR-1414 and 50/125 μm, 62.5/125 μm, 100/140 μm, and 200 μm (HCS) optical fibers, with a maximum communication rate of 5 MB. Due to the use of an open collector circuit, this receiver is compatible with TTL and CMOS levels. The communication distance of this circuit can reach up to 1.7 km.

In order to improve the comprehensive performance of the CAN communication board, such as its anti-vibration and anti-interference properties, a double-sided wiring design is adopted. The size specifications of this communication board are strictly in accordance with the requirements of the PC/104 board.

(3) Redundancy design and CAN Hub design

The communication board is designed with 4 redundancies. When working, only 1 CAN channel is working. The high-bit chip select method is used to select the working channel. The chip select module is designed inside the FPGA.

(4) Design of GAN Hub

Since this system adopts the "dual optical and dual electrical" four-redundancy circuit design, in order to improve the communication speed, the 485 transceiver is used instead of the standard CAN transceiver. Light is a "point-to-point" transmission, and the 485 transceiver is a differential transmission. In form, they cannot form a bus structure. Therefore, the CAN Hub is introduced to process the signal and achieve a bus structure logically.

3 Software design The normal operation of the CAN communication board is inseparable from powerful software support. The core of the control part of this system uses a PC/104 embedded computer system. The PC/104 embedded computer has powerful functions comparable to those of a PC. The

development and design of the CAN communication board software part is completed on the PC/104 computer and is designed in C language. The C language is versatile, efficient and real-time, and can meet the real-time requirements of the instrument. In the design process, a modular and structured design method is adopted to divide the software into several modules according to the function. These modules have certain independence and certain connection. The compilation requirements of each module are relatively independent, so as to test, debug, modify and maintain each module. This framework mode program can ensure good versatility, maintainability, scalability, portability, interchangeability and independence.

Since the internal structure of the CAN core is the same as that of SJA1000, it is simple and convenient to write when developing, just like facing SJA1000. This design uses interrupt processing to process tasks. Just perform corresponding processing after the interrupt arrives.

The communication board initialization process is shown in Figure 3.

The data sending process is shown in Figure 4, and the data receiving process is shown in Figure 5.

4 System simulation

Modelsim is used for simulation.

The system test platform (TestBench) instantiates the module can4core and a CAN core cantop, and simulates the communication between them.

This simulation is carried out completely in accordance with the normal working process of the CAN core. The simulation process is as follows:

① Initialization setting. First, set the time register and the data format. Set the system design module and CAN core through the platform.

② Synchronization test. Including hard synchronization test and resynchronization test. After a hard synchronization, the internal bit time restarts with the synchronization segment. Hard synchronization makes the jump edge that causes hard synchronization located within the restarted bit time synchronization segment.

③ Empty FIFO test (test_empty_fifo_ext). This test receives 2 data frames, then reads the receiving buffer, then clears the buffer, and then reads the buffer, repeatedly clearing and reading to see if the data in the FIFO is completely cleared.

④ Full FIFO test (test_full_fifo_ext). First, clear the register, then fill the FIFO by continuously receiving data frames and read the information to detect whether it can work normally.

⑤Bus-off-test. By continuously sending data to make the bus busy, the bus will generate errors. Test whether the interrupt register can detect errors and whether the CAN core can continue to work normally after the errors are cleared.

⑥Basic CAN mode frame detection. Test whether the CAN core can send frames normally.

⑦Register test. By continuously reading and writing registers, test whether the CAN core registers work normally.

⑧Data transmission on the bus. An important point in the simulation process is whether the data information can be transmitted normally on the bus.

After simulation, it can be seen that the CAN communication board has broken through the speed limit of SJA1000, and the transmission speed can reach 2 MHz. The effective transmission rate has been greatly improved and the working performance is good.

Conclusion

The CAN bus communication board designed in this paper completes the communication conversion between PC/104 and CAN bus, changes the traditional design method of applying CAN controller plus external controller, and on the basis of designing CAN core, all digital signal processing parts in the communication board are placed inside FPGA to realize, so that the communication speed is greatly improved. Whether in terms of transmission rate or anti-interference and anti-vibration, the comprehensive performance of CAN core application has been greatly improved.