Designing the Clock of SDH Optical Transmission System Equipment Using FPGA

SDH Equipment Clock (SEC) is an important part of SDH optical transmission system, the foundation of SDH equipment to build synchronous network, and the premise of reliable operation of Synchronous Digital Hierarchy (SDH). The core component of SEC is composed of phase-locked loop. Network elements track the synchronous timing reference through the phase-locked loop, and filter the jitter and drift of the reference clock during transmission through the filtering characteristics of the phase-locked loop. When the reference source is unavailable, SEC provides local timing reference information to achieve high-quality clock output.

SEC needs to meet the relevant indicator requirements of ITU-T G.813 recommendation [1]. SEC can work in three modes: free oscillation, tracking, and holding, and can switch smoothly between the three modes. Since the SEC bandwidth specified in ITU-T G.813 recommendation is relatively narrow (-3db bandwidth is within 1~10Hz), and it is necessary to output a stable clock in the three working modes, and at the same time ensure that the output clock is stable during the switching process of the three modes (i.e. smooth switching), it is difficult to achieve using an analog phase-locked loop (APLL). Therefore, a digital phase-locked loop (DPLL) is generally used to implement SEC [2]; there are also many chip manufacturers that directly use monolithic integrated circuit chips to implement SEC, such as SEMTECH's ACS8520 [3].

This paper introduces a solution to implement SEC function using a single-chip field programmable gate array (FPGA) chip. The SEC function chip designed using FPGA is named TSP8500.

1 Internal structure and design principle of TSP8500 chip

The TSP8500 chip is implemented using Altera's EP2C5T144-8 FPGA. The internal structure block diagram of the chip is shown in Figure 1.

TSP8500 provides two types of clock output interfaces: ① Providing 38.88MHz system clock sysclkout and 2kHz system frame header signal sysfpout to each functional module in the SDH network element system; ② Providing 2.048MHz external synchronization output reference clock ext_clk_out to other network element devices.

The chip needs to input a 19.44MHz local clock from the outside, and multiply it through the internal PLL (phase-locked loop 1) of the FPGA to get a 311.04MHz high-speed clock as the working clock of the digital phase-locked loop inside the chip. When all reference sources are lost, in order to ensure that the SEC can still output high-quality clocks, the local clock is generally provided by a high-stability temperature-compensated crystal oscillator (TCXO) or an oven-controlled crystal oscillator (OCXO).

The chip also provides a microprocessor interface for selecting the reference source of each digital phase-locked loop, setting the working mode, and querying the internal working status of the chip.

1.1 Design and implementation of system clock

As can be seen from Figure 1, the system clock sysclkout output by the chip is mainly completed by an all-digital phase-locked loop (ADPLL) [4], a master-slave interlock module (actually also an ADPLL) and the FPGA's internal PLL (phase-locked loop 2).

The chip can select any one of the input clocks as the reference clock for tracking. When using the chip, the user sets the priority table of the reference source through the microprocessor interface, and the chip can automatically select the best reference source for phase-lock tracking according to the quality level of the reference source.

The ADPLL designed in the TSP8500 chip is basically the same as other types of phase-locked loop structures, mainly consisting of three parts: phase detector, logic filter and digital control clock generator. SEC requires that high-quality clocks can still be output in the hold mode, so a hold data module is added to the ADPLL used to generate the system clock.

When the system clock works in tracking mode, the ADPLL loop is used to synchronize the output system clock and the reference clock. At the same time, the frequency control word data is stored in the RAM inside the FPGA (i.e., the data retention module in Figure 1). When all reference sources are lost, the SEC enters the retention mode, and the chip takes out the frequency data stored in the retention data module in a first-in, last-out manner, and controls the digital control clock generator, ensuring that the system clock can still output high-quality clocks in the retention mode. [page]

When the system clock works in free oscillation mode, the system clock is obtained by directly dividing the high-frequency clock freely.

According to the ITU-T G.813 recommendation, the SEC bandwidth is narrow (-3db bandwidth is within 1 to 10Hz). In the logic filter module, the digital logic inside the FPGA is used to implement the second-order linear filter, which meets the requirements of the SEC noise transfer characteristics. For flexible application, the loop bandwidth of the filter can be flexibly adjusted through the microprocessor interface. When the reference source is switched, the smooth design of the filter ensures that the frequency control word changes slowly, and the smooth switching of the reference source is reliably achieved.

The digital clock generator module is obtained by controlled frequency division of the high-frequency clock under the action of the frequency control word. In order to reduce the digital phase noise generated by the digital clock generator output clock during the controlled frequency division process, the TSP8500 chip is designed with a unique "micro phase adjustment technology" to make the cycle-cycle jitter of the digital clock generator output clock only 0.4ns.

SEC generally adopts a master-slave backup design. Since the bandwidth of the SEC itself is narrow and the capture speed is slow, when the master and standby SEC track the same reference source, it is impossible to keep the master and standby SEC phase synchronized at all times. A master-slave interlocking module is added to the design to ensure the rapid synchronization of the master and standby phases. The master-slave interlocking module is also implemented by ADPLL, but its loop bandwidth is designed to be wider and the capture speed is fast, which is enough to ensure accurate synchronization of the master and standby phases. When the SEC works in master mode, the master-slave interlocking module directly locks the clock output by the full digital phase-locked loop ADPLL of this board; when the SEC works in standby mode, the master-slave interlocking module locks the system clock RDSYSCLK sent to the other board.

The clock output by the master-slave interlock module still has a phase jitter of 0.4ns. Here, the phase is smoothed by the FPGA's built-in PLL (phase-locked loop 2).

The system frame header of the main board is directly obtained by freely dividing the 38.88MHz clock of the main board. The system frame header of the standby board is generated by dividing the system clock of this board under the control of the synchronous frame header sent by the main board. Since the phases of the main and standby system clocks are synchronized, the phase synchronization of the system frame header is guaranteed.

1.2 Design and implementation of external synchronous clock

The external synchronous clock ext_clk_out output by the chip is realized by one ADPLL.

The external synchronous clock can be selected from the input clock or system clock as the reference clock for tracking; the source is selected through the microprocessor interface.

The filter design of the external synchronous clock loop is also directly implemented by the digital logic inside the FPGA, but the loop bandwidth is designed to be relatively wide. When the reference source is switched, the ADPLL will briefly enter the hold mode to ensure the stability of the output clock.

Since the external clock frequency is 2.048MHz, which cannot be obtained by integer division of the 311.04MHz clock, the digital control clock generator module adopts a fractional controlled frequency division design. Due to the use of fractional frequency division, the phase jitter of the external synchronous clock output by the digital control clock generator is 0.8ns.

Due to the PLL resource limitation of FPGA, the external synchronous clock is not filtered by APLL but directly output by the digital control clock generator. However, the phase jitter of the output clock can far meet the requirement of less than 0.05UI.

2. Output clock performance test

The indicators of the system clock and external synchronous clock output by the TSP8500 chip are tested. The following mainly gives the jitter characteristics of the clock and the phase drift characteristics of the SEC in the lock mode and the phase drift characteristics of the SEC in the hold mode.

2.1 Output Clock Jitter Characteristics

Set the high-speed oscilloscope to the "long afterglow" mode, test the signal waveforms of the system clock sysclkout and the external synchronous clock ext_clkout output by the TSP8500, and obtain the PP jitter characteristics of the output clocks. The PP jitter of the sysclkout clock is less than 100ps; the PP jitter of the ext_clkout clock is less than 2ns.

2.2 Phase drift characteristics of SEC

The test method is shown in Figure 2.

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Rubidium clock is used as the test clock reference source. The reference clock is sent to TSP8500 for tracking and also to the time interval analyzer.

The reference source of the system clock sysclkout of TSP8500 is the 2.048MHz clock sent by the clock reference source through the CPU interface. Since the system clock sysclkout output is 38.88MHz, it is not convenient to test it with a time interval analyzer, so the external synchronous clock ext_clk_out interface is used to output a 2.048MHz clock to send to the time interval analyzer for TIE curve testing; and the reference source of the ext_clk_out clock is the sysclkout clock selected through the CPU interface.

In the tracking mode, the switch K in FIG. 2 is closed, and the MTIE/TDEV curve obtained after the test for 24 hours is shown in FIG. 3 .

From the test conclusion of Figure 3, the phase drift characteristics of TSP8500 in tracking mode meet the requirements of ITU-T G.813 recommendation.

After 24 hours of tracking, the switch K in FIG2 is disconnected, and the system clock of TSP8500 automatically enters the hold mode. The time interval analyzer is used to test for 24 hours to obtain the MTIE/TDEV curve in the hold mode, as shown in FIG4 .

From the test conclusion of Figure 4, the phase drift characteristics of the TSP8500 chip in the hold mode also meet the requirements of ITU-T G.813 recommendation.

The SEC chip TSP8500 implemented with a single FPGA has an output clock that meets the requirements for its application in SDH equipment, and all clock performance indicators fully meet the relevant recommendations of ITU-T G.813. The TSP8500 chip has been used in SDH equipment developed by a well-known domestic communication equipment manufacturer.

In addition, the FPGA used in the TSP8500 chip costs less than $10, which is much lower than the price of commercial SEC chips. It is reliable in function and has a very high cost-performance ratio, and is expected to be used commercially on a larger scale.