IP Core Deliverables

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IP Core Deliverables [Copy link]

IP Core Deliverables

When a company buys a license for an IP core, it typically receives everything it needs to design, test, and use the core in its own products. IP core designs are usually provided in a hardware description language, HDL, similar to a computer software program. Logic and test patterns and signal specifications may also be provided. Any software required is usually included, as well as design notes and documentation about known bugs.

Since IP cores are divided into soft cores and hard cores, IP providers also need to provide different codes, scripts, software, data, reports and other types of records and documents for these two different types of IP cores.

Soft IP Core Deliverables

Product Documentation

Compilable Verilog/VHDL code at behavioral and/or RTL (Register Transfer Level) level.

Corresponding compilation script (Tcl) and synthesis constraint file (SDC).

Compile Report

Scripts for scan insertion and ATPG (Automatic Test Pattern Generation and Automatic Test Pattern Generator) (optional)

Floorplanning shells and constraints (optional)

Place & route script (optional)

Installation guide and scripts (optional)

Design notes and documentation on known bugs

Application note including VHDL/Verilog design example that instantiates the core.

Design Examples - Reference (synthesized) designs for reference libraries (provided by CIC - Cascaded Integrator Comb) and corresponding area, timing, power, testability reports.

Verify the file

All deliverables shall be fully tested and shall have the following characteristics:

System-level verification and testing strategy

Verification/simulation models/environment and test bench (test patterns) scripts and test suites with expected results/test reports.

Test planning/guidelines/methods and testability measurements

Vectors used to test core functionality

Code Coverage Report

CDL (Circuit Design Language) for LVS (Layout and Schematic) verification.

Functional verification model (optional)

Behavioral models for simulation.

Suitable functional model

Simulation model (optional)

Basic delay model.

BFM (Bus Functional Model) and Bus Monitor used in the test bench

Documentation Files

Functional specifications, descriptions and architectures

Key features and announcements

Comprehensive technical specifications and data sheets

Configuration information and parameters

User Guide/User Manual.

Validation Plan/Guidelines

Integration Guide

Hard IP Core Deliverables

Product Documentation

Optimized netlist format

GDSII (Graphics Data Stream II) layout view integration.

SPICE Netlist (.cdl)

Constraints File

Place & route script

Layout related information (timing, power, delay, area, etc.)

Installation Script

Design Examples

Verify the file

All deliverables will be fully tested and characterized by the IP provider.

Test report.

Self-checking test bench

Test vectors for testing the core

constraint

Instantiating a Template

High fault coverage test vectors

Documentation Files

Functional specifications

Data Sheet

User Guide

Integration Guide

Testing Guide

Test Modes for Manufacturing Test

Test vector,

Evaluation kits based on packaged ICs

Characterization Report

Integration Support

System Integration Documentation

ISA (Instruction Set Architecture) or behavioral model

Bus functional model

Cycle Accurate Model

Sign-off Model

Timing and Synthesis Models

Physical (floor planning) model

Optional simulation models

.lib, .lef, etc. timing models

Recommended commercial software for hardware/software co-simulation and system integration for specific hard IP

Test mode for manufacturing testing (if applicable)

Contents of the User Guide

Architecture and functional description

Statements and Assumptions

Detailed I/O Description

Exceptions to the Design and Coding Guidelines

block diagram

Register Map

Timing Specifications

Timing diagram

Area/Performance/Power

DFT and Test Coverage

Size/Number of Doors

Configuration and parameters

Test structure, testability, and test coverage

Recommended Clock and Reset Strategy

Recommended software environment, including compilers and drivers

Recommended System Validation Strategy

Recommended Testing Strategy

Floor Plan Guide

Debug strategies, including in-circuit emulation and debugging tools

Version history and known bugs

Fred_1977

This refers to knowledge related to FPGA design, right?

wsmysyn

Fred_1977 posted on 2022-2-19 09:04 Does this refer to knowledge related to FPGA design?

Chip IP, one provides RTL, which can be simulated on FPGA, and the other is GDSII file, which can only be merged in the foundry