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Latest update time:2019-03-15
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The 5G revolution is coming. Whether it’s faster, richer content in the form of seamless augmented and virtual reality experiences or the technology to enable truly self-driving cars, it promises to inspire a host of innovations and new services.

Driven by the rapid development of the telecommunications industry, there is a huge demand for higher bandwidth and faster data rates, requiring serious network upgrades. The Ethernet backbone that transmits information from end users to the central core network through a complex interconnection of switches and routers has undergone tremendous changes, from 10 Mbps to the current 400 Gigabit Ethernet speeds and greater than 1 Terabit Ethernet in the future.

At the heart of every 5G and 400Gbps node is a semiconductor timing integrated circuit (IC) called a network synchronizer. The synchronizer ensures the accuracy of sampled information, thereby reducing bit errors and link impairments.

The breakthrough technology that helps achieve ultra-low jitter (noise) on the output clocks of these network synchronizers is called bulk acoustic wave (BAW) resonators.



TI BAW resonator technology for timing

Learn how TI's BAW clock technology reduces vibration and simplifies designs in next-generation communications systems.

Figure 1 shows the packet-switched telecommunications network ecosystem, which includes 5G wireless infrastructure and 400-Gbps switches and routers that transfer data between the network edge and its core.

Figure 1: Packet-switched telecommunications network

A BAW resonator is a high quality factor (high-Q) resonator that replaces the traditional inductor-capacitor oscillator commonly found in network synchronizer ICs. It is a thin film resonator similar to a quartz crystal, sandwiched between a metal film and other layers to confine mechanical energy. The result is a high-Q, ultra-low noise resonator with unmatched performance.

Why is this performance critical for 5G and 400-Gbps networks?

400-Gbps transceivers use a four-level pulse amplitude modulation (PAM-4) scheme to transmit data. This data modulation scheme enables higher data rates over the same bandwidth compared to traditional non-return-to-zero modulation schemes. 400-Gbps standards like the Optical Internetworking Forum Common Electrical Interface and the Institute of Electrical and Electronics Engineers 802.3bs have very stringent transmit jitter requirements for PAM-4 transmitters, allocating only a small fraction of the overall transmitter jitter to the network synchronizer to generate the reference clock.

Application-specific IC vendors for switches using 56G PAM-4 serializer/deserializer (SerDes) solutions require a maximum integrated reference clock jitter of 150 fs root mean square (RMS) in the 12 kHz to 20 MHz band. Network synchronizer clocks using TI BAW resonator technology, such as the LMK05318, typically have an integrated RMS jitter (12 kHz to 20 MHz) of less than 60 fs (156.25-MHz carrier), as shown in Figure 2. This level of performance can help designers future-proof their systems.

Figure 2: Clock from the LMK05318 network synchronizer

156.25 MHz output clock

Now, regarding radio in 5G applications, the 5G New Radio standard specifies new frequency bands below 6 GHz and extends to millimeter wave frequencies. While below 6 GHz is an advancement of existing Long Term Evolution (LTE)-Advanced capabilities, the real challenge lies in millimeter wave designs, where more continuous bandwidth is available to transmit large amounts of data. Reference clock impairments (e.g., phase noise) can cause distortion of the modulated signal, which becomes a problem at the higher frequencies and wider bandwidths characteristic of millimeter wave designs.

Signal quality is characterized by the system’s error vector magnitude, which is primarily affected by the phase noise of the reference clock. As denser modulation schemes are planned for 5G (from 256 quadrature amplitude modulation [QAM] today and up to 1,024 QAM in the future), the requirements for error vector magnitude become increasingly stringent. Therefore, a low-noise reference clock from a network synchronizer is critical to ensure optimal system performance.


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