Why do I need a low jitter clock when evaluating high performance ADCs?

Typically, it requires a function generator capable of up to 1nsRMS jitter. A high-quality RF generator or crystal oscillator is often required to obtain the best SNR values ​​from a 16- or 18-bit ADC, even at relatively low input frequencies. In this article, I will use the DC1826A-A demo board with the LTC2389-18 2.5Msps 18-bit ADC and LTC PScope software installed to illustrate the effects of jitter on SNR performance and how to reduce jitter on a noisy clock source.

As a baseline, the clock input of the DC1826A-A was driven with a Rohde & Schwarz SMB100A RF generator, with the analog input provided by a Stanford Research SR1. The result is the PScope data in Figure 1, which produces a 98.247dBFS SNR.

Figure 1: Baseline FFT showing 98.247dBFS SNR for the LTC2389-18

This SNR is obtained by adding a less than full-scale input level (-1.047dBFS) to the measured SNR. The 18.8psRMS jitter at the CNV input of the ADC can be measured using an Agilent Infiniium 9000 Series oscilloscope or equivalent. The theoretical limit for SNR based on jitter and input frequency is

in:

tjitter is the RMS jitter

fIN is the input frequency

Substituting the values ​​for this example yields an SNR of

This value must then be RMS summed with the ADC SNR to produce an effective SNR. Looking at the LTC2389 data sheet, the typical SNR used for the demo board circuit (Figures 7a and 7b) is 98.8dB at 2kHz.

LTC2389 data sheet, Figures 7a and 7b

The “SNR vs. Input Frequency Curve” given in the product manual shows that at the 20kHz input frequency used in this experiment, the SNR rolls off by about 0.3dB, so the 98.8dB figure will be adjusted to 98.5dB. The RMS sum of 98.5dB and 112.5dB is 98.3dB, which is close to the result obtained in Figure 1.

Figure 2: RMS jitter at the CNV input of the DC1826A-A (using the SMB100A clock source)

Now that we have a baseline SNR measurement, what happens if we use a clock source with higher jitter? As shown in Figure 3, the jitter measured when using the XXXX-YYYYY (manufacturer and model number withheld) generator is 76.5psRMS. The theoretical limit for SNR at this jitter level is 100.3dB, which when RMS summed with the LTC2389-18’s 98.5dB gives a result of 96.3dB.

Figure 3: A noisy clock source produces 76.5psRMS jitter at the CNV input of the DC1826A-A

The 96.2dBFS measured SNR shown in the PScope screenshot of Figure 4 is in good agreement. At the relatively low 20kHz input frequency, the SNR specification is degraded by 2dB, with less than 60ps of added clock jitter. At a 100kHz input frequency, the SNR drops to 86dB.

Figure 4: The SNR of the LTC2389-18 degrades to 96.2dBFS when using a noisy clock source

Using the previous clock source, a TTE low-pass filter was inserted between the clock output and the demo board clock input. The measured clock jitter was reduced to 54.7psRMS (as shown in Figure 5), while the resulting SNR was improved to 96.8dBFS (as shown in the PScope screenshot in Figure 6).

Figure 5: Low-pass filtering of a noisy clock source reduces jitter at the CNV input

Figure 6: Low-pass filtering of a noisy clock source slightly improves SNR

虽然取得了小幅改善，但其仍然不如基线 SNR 测量结果那么好。接着，插入一个 TTE 带通滤波器以替代低通滤波器。现在，测得的时钟抖动为 16.7psRMS (如图 7 所示)，而 SNR 的测量结果则显著地改善至 98.3dBFS (如图 8 给出的 PScope 截屏所示)。测得的 SNR 此时与基线 SNR 测量值相同。

Figure 7: TTE bandpass filter greatly reduces jitter

图 8：TTE 带通滤波器显著地改善了 LTC2389-18 的 SNR 指标

It is now easy to understand the necessity of using a low jitter clock source when evaluating high resolution ADCs. If the clock source you have available does not have low enough jitter, you can still get good SNR measurements by filtering the clock with a good bandpass filter.