Common control modes of switching power supplies (peak current, average current, current hysteresis)

The switching converter controller (chip) is the core of the DC-DC converter and can be divided into two categories: PWM control chip and PFM control chip. The main function of the PWM control chip is to generate a pulse signal with a fixed frequency and a pulse width that changes with the input and output voltage of the converter to control the conduction time of the switch tube in the converter, so that the output voltage of the DC-DC converter remains stable; and The main function of the PFM control chip is to generate a pulse signal with a fixed low-level time or a fixed high-level time, but the switching frequency changes with the input and output voltage of the converter to control the conduction time of the switching tube, thereby making the DC-DC converter output The voltage remains stable. One is fixed frequency, the other is variable frequency, variable and unchanged control logic;

According to the different sampling objects, PWM controllers can be divided into two categories: voltage type and current type. In order to simplify the peripheral circuits of different topology converters, many semiconductor manufacturers have designed corresponding PWM control chips or PFM control chips for different topology converters. Among them, traditional hard-switching flyback and forward converters can share the same type of PWM control chip. Such as UC384X series chips, FAN67XX series and On-Bright's OB2262, OB2263, OB2273, etc.; traditional hard-switched half-bridge and full-bridge converters can also share the same type of PWM control chip, such as TL494 and its compatible chips KA7500, SG3525 chips, etc. ; And PFM control chips such as FAN7930, L6562, MC33262, OB6563 are specially designed for APFC converters; QR flyback converters have dedicated QR control chips, such as Fairchild's FAN6300 series (including FAN6300A, FAN6300H), ON Semiconductor's NCP1207 , NCP1380 series, Angbao's OB2201, OB2202, OB2203, etc.; half-bridge resonant LLC converters also have dedicated PFM control chips, such as ST's L6599 and L6599A, Fairchild Semiconductor's FAN7621, FAN7631, etc., which have been merged into ON Semiconductor.

1. VM voltage PWM controller

It is composed of output voltage sampling circuit, error amplifier EA, comparator CP, oscillator OSC, sawtooth wave generator and SR flip-flop that assumes the level latch function.

Figure 1 PWM VM power boost controller block diagram

Working principle: The duty cycle wave size is sampled by the output voltage Uo, and the PWM duty cycle is controlled to stabilize the output voltage. In the VM PWM controller, the switching frequency of the oscillator is fixed, and the slope of the sawtooth wave output signal is It is also fixed. The PWM regulator is actually a voltage comparator. The output signal Uc of the error amplifier EA is an analog signal controlled by the output voltage. When the input voltage increases, VC decreases, otherwise it increases. The oscillator clk The output is high level, and the RS flip-flop Q is set high, which is equivalent to sending out waves on the rising edge of the clock. When will it stop sending out low levels? Controlled by the R terminal, the R terminal becomes low, stops sending waves, and then sends waves again at the next rising edge of the clock; the high level of the duty cycle starts from CLK, and finally R becomes low, and the period of the entire cycle clk is fixed, accounting for The time when the space ratio becomes low is the comparison between VC and the ramp wave. When the ramp wave is greater than VC, the wave generation stops; see the middle waveform in Figure 1 for details.

Advantages: The voltage controller does not require a slope compensation circuit and only has a closed-loop feedback loop.

Disadvantages: However, the design of the feedback compensation circuit is relatively complex, and the biggest disadvantage is the slow response to changes in the input voltage UIN. For example, when the input voltage UIN undergoes a step jump, the output voltage UO may fluctuate significantly because the converter output terminal is connected to a large-capacity filter capacitor. After a period of time, the output voltage UO gradually becomes stable. Therefore, it may be necessary to add a feedforward circuit in the voltage-type PWM controller to force the sawtooth voltage slope to increase as the input voltage UIN increases, which is equivalent to reducing the duty cycle. When the slope increases, it takes a short time to reset. , plays a feed-forward role; for example, TI's controller UCC3750 buck controller VM control has a feed-forward role; early compensation, feed-forward compensation, can make the duty cycle irrelevant to the input voltage, making compensation easy.

2. Current type controller CM

Switching power supply technology and design of current mode control In order to improve the dynamic response speed of the switching controller, FC Shiwarz proposed the current mode (Current Mode Control) controller model in 1972. It is actually a current and voltage double closed-loop negative feedback control system. With the help of voltage Closed-loop negative feedback stabilizes the output voltage in order to obtain good load regulation; the feedforward characteristics formed by closed-loop negative feedback of the main switch inductor or switch tube current improve the response speed of the input voltage mutation in order to obtain good line voltage regulation. Current-mode controllers include three methods: peak current control, average current control, and current hysteresis control.

Figure 2 CM PWM BOOST block diagram

Working principle: double closed loop, outer loop voltage loop, inner loop current loop; by sampling the output voltage, controlling the duty cycle of the PWM signal to stabilize the output voltage, and by sampling the inductor current, changes in the input voltage can be sensed instantly. In the current-type PWM controller, the oscillation frequency is also constant. The EA output UC amplitude of the error amplifier determines the output voltage. When the switching tube Q1 cuts off the device, the sampling signal is 0. The non-inverting input section of the CP comparator Wie0, the inverting input Segment Uc is greater than 0, so the R terminal is 0, and the flip-flop is active high. When the oscillator OSC is high level, it triggers S=1, Q value=1, and turning on MOS Q1 is equivalent to the clock opening the door. Closing the door is on the RS detection resistor. The current ramp amplitude is determined. When it is greater than UC, the high level R=1, Q=0 is triggered, Q1 is turned off, ton ends, and enters tooff. When the next rising edge of the clock arrives, the next ton moment is turned on, and the cycle begins again. The RS flip-flop has two functions (trigger and hold functions. S=1 triggers on, R=1 triggers reset, and is held at other times);

Advantages: Since the inductor current IL=uin/L*T and the voltage waveform on the detection resistor US=IL*RS=uin/L*RS*t, it can be seen that the slope of the slope is affected by the input voltage and is proportional to it. It has the voltage front Feedback characteristics, the response speed to the mutation of the input voltage Uin is fast, and the constant current source control is used. Compared with the VM control, the compensation is easier. Generally, type 2 compensation or basic type 1 compensation is required to achieve stability; as shown in Figure 3, the output The duty cycle adjustment process when the voltage increases and decreases and the input voltage decreases. It can be seen that when the input voltage decreases, the duty cycle is directly changed to maintain the stability of the inductor current, so the corresponding adjustment is faster than the VM adjustment. More suitable for wide voltage input topology.

Figure 3 Adjustment waveform of current-mode PWM controller

The disadvantage is: when CM turns on Q1, the parasitic capacitance of the transformer is instantly charged through the MOS, causing its leading edge voltage spike. Generally, RC filtering is required to avoid it, or there is filtering or delay counting in the controller to avoid it. In addition, its duty cycle is such as Greater than 0.5 CCM, there is sub-harmonic oscillation and slope compensation is required; for DCM mode, it is not required.

3. Peak current controller sub-resonance phenomenon and slope compensation circuit

When working in CCM mode, sub-resonance phenomenon occurs when the duty cycle D>0.5; the specific manifestation is that the system is disturbed, the input voltage suddenly changes and then recovers, the load changes suddenly and then recovers, etc. The two adjacent switching cycles will be affected by the change of the inductor current. The offset causes the TON conduction time to alternate, causing the system to enter an out-of-control state. Especially when large and small waves appear during testing, oscillations with a lower switching frequency than normal occur, which is the so-called sub-harmonic oscillation phenomenon.

The details can be explained vividly in Figure 4. The thick solid line represents the ramp voltage under normal conditions, and the dotted line represents the ramp voltage after interference.

Figure 4 CCM D>0.5 harmonic phenomenon D<0.5 disturbance is reduced

In the figure, the BOOST inductor current IL is sampled by the detection resistor as a current ramp signal. The turn-on ramp US=IL*RS=uin/L*RS*t increases linearly with the turn-on time. The converter is disturbed after the first Within K cycles, the inductor current increases linearly from the minimum value to IL'. For example, if the load suddenly decreases and then recovers quickly, or the input voltage suddenly increases and then recovers, etc., it will cause IL' to decrease, and the controller's ton increases to Ton' in the Kth cycle. Logically speaking, it should return to the normal value after several cycles. However, this small disturbance causes the duty cycle to be greater than 0.5, and the time after K+1, K+N, TOn is shortened. , and so on, causing the system to enter an unstable state and form sub-harmonic oscillation. In DCM and CRM modes, because each cycle IL starts from 0, this problem does not occur. Only the disturbance affects the current switching cycle. The duty cycle increases or decreases; when the duty cycle is less than 0.5, high school geometric principles can easily prove that the duty cycle increment gradually decreases and the disturbance becomes smaller;

For this reason, in the DC-DC converter composed of a peak current PWM controller, in order to avoid the sub-resonant phenomenon of the peak current PWM controller in CCM mode when the duty cycle D>0.5, the control of the comparator can be The voltage UC shows a downward slope, or a harmonic is added to the non-phase end of the current detection. (A slope compensation voltage of the same frequency is superimposed on the slope voltage corresponding to the inductor current to increase the equivalent slope voltage slope.) The purpose is to reduce For small duty cycles, this actually involves introducing a harmonic to handle the duty cycle disturbance;

Figure 5 Current ramp compensation

(1) If the converter operates in CCM mode, limiting the duty cycle to less than 0.5 can avoid sub-resonant phenomena;

(2) At the minimum input voltage, when the duty cycle D may be greater than 0.5, if the DCM or BCM mode is selected, there will be no sub-resonance phenomenon;

(3) At the minimum input voltage, the duty cycle D may be greater than 0.5, and when the converter must work in CCM mode, the slope compensation circuit can only be used to avoid sub-resonant phenomena and ensure stable operation of the converter.

The ASAP peak current type control strategy has a slope compensation circuit under specific conditions, but its advantages are very obvious. It eliminates the double pole of the inductor, reduces the LC transfer function of the system to the first order, and makes loop stability compensation easier. In addition, the line The adjustment rate is improved and the response to the input voltage is fast. It is easy to implement CBC cycle-by-cycle current limiting protection, which simplifies the overcurrent protection circuit design. When multiple modules are connected in parallel, the reference of each module comes from the input voltage reference VC, which is easy to To achieve parallel current sharing, most current-type flyback and forward converter Pwm control chips currently use this control method.

4. Average current type control

This control mode is the average current type control proposed by BLWILKINSON in 1987. This control scheme has been widely used in PFC circuits. As shown in Figure 6 below

Figure 6 Average current control BOOST block diagram

Its working principle: UO sends the inverting input terminal of the error amplifier through FB through input sampling, and the signal VE after amplification and compensation of the reference voltage error is used as the reference signal of the inner loop current loop. This is the same as the previous VM and peak CM control. In the outer loop, VE serves as the reference for the average current of the inner loop, the peak current CA is the comparator, and this average current is the current error amplifier, which amplifies the difference between the inductor current IL and UE to generate a VC signal. The VC signal is then cut with a sawtooth wave to generate PWM. It can be seen that the average current control signal is also a double closed-loop control system of voltage and current;

Advantages: This average current control has strong anti-interference ability and high stability. Disadvantages: the inductor average current sampling circuit is complex, the detection element is large in size and consumes large power;

5. Current hysteresis control

Current hysteresis control also samples the inductor current and compares it with the given upper limit current and lower limit current of the inductor. When the inductor current of the converter is greater than Ilmax, the PWM outputs a low level, causing the switch to turn off and the inductor current to drop. When it drops below Ilmin, the switch turns on; in this way, due to the rise and fall of the inductor current The slope is related to the load and input voltage. Therefore, the switching frequency of current hysteresis control is not fixed and will change with the load and input voltage. It belongs to the modulation category of PFM.

Of course, the above are classic control modes, which are not limited to these types of control, but also include charge control, single-cycle control, digital PID control, etc. Analysis can be performed based on the design pattern of the controller.

This article explains PWM VM and CM (peak, average), PFM (COT control mode) classic control methods. It is a commonly used working method and is widely used.