1 Causes of subharmonic oscillation
Taking the PWM modulated peak current mode switching power supply as an example (as shown in Figure 1, and the down-slope compensation structure is given), the causes of subharmonic oscillation are analyzed in detail from different angles.
For the current inner loop control mode, Figure 2 shows the change of the inductor current when the system duty cycle is greater than 50% and the inductor current undergoes a small step ΔA. The solid line is the inductor current waveform when the system is working normally, and the dotted line is the actual working waveform of the inductor current. It can be seen that: 1) the inductor current error of the next clock cycle is larger than the inductor current error of the previous cycle, that is, the inductor current error signal oscillates and diverges, and the system is unstable; 2) the oscillation period is twice the switching period, that is, the oscillation frequency is 1/2 of the switching frequency, which is the origin of the name of subharmonic oscillation. Figure 3 shows the change of the inductor current when the system duty cycle is greater than 50% and the duty cycle undergoes a small step AD. It can be seen that the system will also have subharmonic oscillation. When the system duty cycle is less than 50%, although the disturbance of the inductor current or duty cycle will also cause the inductor current error signal to oscillate, this oscillation is a decaying oscillation. The system is stable.
The causes of subharmonic oscillation have been qualitatively analyzed above, and now we will quantitatively analyze them. For Figure 1, Figure 4 shows the changes in the inductor peak current error signal caused by duty cycle disturbance, where Vc is the output signal of the error amplifier. When the power tube MO is turned on, that is, the inductor current rises linearly, Vc increases accordingly. Conversely, when the power tube M0 is turned off, Vc decreases accordingly. It can be seen from Figure 4 that when the duty cycle is asymmetric under two consecutive clock pulses, subharmonic oscillation will occur in the system. The relationship between △Vc and △IL is now derived. The changes in the inductor current and the error amplifier output voltage caused by the duty cycle disturbance △D are shown in equations (1) and (2), respectively. From equations (1) and (2), the relationship between Vc and △IL can be derived as shown in equation (3):
Where: T is the switching period; m1 is the peak current rising slope; m2 is the absolute value of the peak current falling slope; seven represents the sampling resistor.
Since the subharmonic oscillation frequency is 1/2 of the switching frequency, the voltage loop gain at 1/2 of the switching frequency will directly affect the stability of the circuit. Now derive the voltage loop gain of Figure 1. After adding slope compensation to the output of the error amplifier, assume that the error voltage changes from △Vc to △Ve, and then the relationship between △Vc and △Ve can be deduced, as shown in equation (4). Equation (5) can be obtained from equations (3) and (4), and equation (6) can be deduced in steady state. Substituting equation (6) into equation (5) and eliminating m1, equation (7) is obtained:
Where: m is the slope of the downslope; 2 means that the subharmonic oscillation period is twice the switching frequency.
From Figure 4, it can be seen that △IL is a square wave with a period of 2T, so the amplitude of the first subharmonic should be multiplied by 4/π. Assuming the load capacitance is C, the small signal voltage gain from the output of the error amplifier to the output of the power supply is
Assuming the error op amp voltage gain is A, the voltage outer loop gain is
From the loop stability condition, we know that at 1/2 switching frequency, the loop phase margin is zero. At this time, if the loop gain is greater than 1, subharmonic oscillation will occur in the system. Therefore, the maximum gain of the error amplifier is:
(8)
It can be clearly seen from formula (8) that the maximum gain of the error amplifier is a function of the duty cycle D and the slope compensation slope m. The relationship between the normalized maximum gain of the error amplifier and D and m is shown in Figure 5. It can be seen that: when m=0 (no compensation), since the amplifier gain cannot be less than 0, when the duty cycle is greater than or equal to 50%, subharmonic oscillation will occur in the system; when m=-m2/2, subharmonic oscillation will occur only when D=100%, but in the actual circuit, oscillation will occur when D<100%; when m=-m2, the maximum gain of the error amplifier has nothing to do with the duty cycle. When m continues to increase, it has little effect on the stability of the loop, but overcompensation will affect the transient response characteristics of the system.
The above article studies the causes and solutions of subharmonic oscillation caused by the waveform of the inductor current signal change. Now we will study it more deeply from the perspective of the s domain (or frequency domain). Assume that the sampled inductor current i is converted into voltage through the sampling resistor Rs, i(k) represents the current disturbance at the kth clock, △Ve(k+1) is the voltage control disturbance at the k+1th moment, and the discrete time function of the sampling and holding is obtained:
From equation (10), we can see that when there is no slope compensation and m1
Where s is the frequency. esT can be approximated by PadE can be approximated by Pade in the second order:
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Where Qs=2/[π(2/α-1)], that is, the damping coefficient is 1/Qs=[π(m1-m2+2m)]/[2(m1+m2)]. Formula (13) is the current loop transfer function. Before slope compensation, when m1
2 Slope compensation method and circuit implementation
The previous article studied the causes of subharmonic oscillation from several aspects, and pointed out that slope compensation can prevent the system from subharmonic oscillation. Now we study the compensation method and its specific circuit implementation. The slope compensation of the switching power supply is divided into two methods: upper slope compensation and lower slope compensation. Figure 6 shows the principle of lower slope compensation, and gives the inductor peak current waveform with a duty cycle greater than 50% during lower slope compensation (a small current disturbance is used as an excitation signal). Compared with Figure 2, only Ve is changed from a horizontal straight line to a lower slope. It can be seen from Figure 6 that after the introduction of slope compensation, the amplitude of the current error signal decays proportionally after each clock cycle and finally disappears. Figure 7 shows the principle of upper slope compensation, and gives the inductor peak current waveform with a duty cycle greater than 50%. The compensation principle is to superimpose the upper slope compensation current b on the inductor peak current a to form a detection current c, so that the duty cycle is less than 50% and the system is stabilized. Since the upper slope compensation circuit is relatively simple to implement, the upper slope compensation is generally used.
For slope compensation, the larger the slope, the faster the oscillation decays, but if the compensation slope is too large, it will cause overcompensation. Overcompensation will aggravate the impact of slope compensation on the system switch current limit index, thereby reducing the system's load capacity; on the other hand, overcompensation will affect the system's transient response characteristics. Usually, the selection of the slope compensation slope needs to be compromised according to needs. For Buck and Flyback converters, the compensation slope is generally taken as the peak current drop slope m2, that is, Vout/L. Since the output voltage is constant, the compensation value is easy to calculate and constant; for Boost circuits, the compensation slope is also generally taken as the peak current drop slope m2, that is, (Vout-Vin)/L. However, since the input voltage changes with the power grid, the compensation value is required to follow the change of the input voltage. At this time, if the slope slope is forced to be fixed for the sake of simple circuit design, overcompensation or undercompensation may occur, reducing circuit performance and causing waveform distortion.
Since the slope compensation principle circuits of Buck and Flyback converters are basically the same, this paper only gives a Flyback slope compensation circuit with upper slope compensation (as shown in Figure 8). Figure 9 is a self-regulating slope compensation circuit for a boost converter proposed by the second author of this paper. Hspice simulation software was used to simulate Figures 8 and 9, and the simulation results are shown in Figures 10 and 11, respectively. The oscillator frequency of Figure 10 is 100 kHz. m1 is the detection current curve, which slowly rises from 0 to 40μA. The dotted lines a, b and c represent slope compensation signals with different slopes, and lines A, B and C are superimposed curves. It can be seen from Figure 10 that by changing the ratio of resistors R5 and R4, compensation signals with different slopes can be obtained. In Figure 11, Vsense is the voltage generated by the peak current on the inductor flowing through the detection resistor, and Vslope is the voltage generated by the detection current flowing through the detection resistor after upper slope compensation. It can be seen from FIG. 11 that different input voltages correspond to different compensation slopes, and the slope change is proportional to the change of (Vout-Vin), thus achieving a self-regulating function.
3 Conclusions
This paper systematically studies the subharmonic oscillation of the peak current mode switching power supply from two perspectives, qualitative and quantitative. When the duty cycle is greater than 50%, the current loop of the system oscillates at 1/2 switching frequency. The introduction of slope compensation can ensure that the transfer function of the current loop gain has a good phase margin at 1/2 switching frequency, ensuring system stability. Finally, two methods of avoiding subharmonic oscillation, upper slope compensation and lower slope compensation, are analyzed, and specific slope compensation circuits and simulation results are given based on the three most basic switching power supply topologies (Buck, Flyback and Boost).
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