Design and simulation of inout port circuit in Verilog

1nnocent

Design and simulation of inout port circuit in Verilog [Copy link]

 

// Module function description
// When the direction control signal "wr_" is "1", y_ is used as output and its value is the value of input signal a_
// When the direction control signal "wr_" is "0", y_ is used as input and the output signal b_ value is the value of signal y_

module bidirection_gate1(
	input			a,
	input			wr,
	output			b,
	inout			y 
    );
    assign y = wr ? a : 1'bz;
    assign b = wr ? 1'bz : y;
endmodule

Writing simulation stimulus files: When I first learned about FPGA, I found that there were inout ports. I was confused when writing simulation stimulus files. Should I define the port as a reg type for input or a wire type for output? Here is a record of the learning process

First, define the input ports of the module to be tested as reg type and the output ports as wire type. Then define the inout port type as reg and define a wire type register mapping for each inout port.

Now let's look at this example: input ports a and wr are set to reg type, output port b is set to wire type, inout port y is set to reg type, and a wire type register mapping y_wire is configured. :

Assign initial value to input signal:

Assign values to the wr enable signal and inout port (here is the key point):

It goes without saying that the enable signal wr changes state every 100, which is convenient for viewing the test signal in each state. y_wire is an inout port, which needs to be passed to the inout port of the module under test. According to the functional description, when wr is 1, the inout port is used as an output and its state needs to be changed to a high impedance state; when wr is 0, the inout port is used as an input, and its value y is our stimulus signal.

Next, simulate:

Waveform signal, a is input, b is output, wr is input control signal, y (note that this y is not that y, this y is just our excitation signal y, not the y of the incoming module), y_wire is the signal of the incoming module y port. From the simulation waveform, we can see that when wr is 1, the inout port is used as output, and the output value is the value of a. From the waveform, we can see that the output inout port is output (that is, y_wire is output), and its value is consistent with a; when wr is 0, the inout port is used as input, and its output value is y (that is, the value of the excitation signal y waveform we gave, and the output port is b at this time). When wr is 0, it can be seen from the waveform that the output signal b, the value of the inout port as the input signal y_wire is consistent with y.

The following is the simulation test file:

// bidirection_gate
module tb_train_demo();
	// inputs
	reg		a;
	reg		wr;
	// outputs
	wire		b;
	// inout
	reg		y;
	wire	y_wire;
	
      
bidirection_gate1 u_bidirection_gate1(
	.a(a),
	.wr(wr),
	.y(y_wire),
	.b(b)
    );
    
	initial begin
		a = 0;
		wr = 1;
		y = 0;
		while(1)begin
			#5;
			a = {$random};
			y = {$random};
		end
	end
	always #100 wr = ~ wr;
	assign y_wire = wr ? 1'bz : y;
endmodule

1nnocent

Use Verilog to change the background color of ID photos

wangerxian

The inout of FPGA is indeed not easy to understand. The SDA of IIC is in this mode.

1nnocent

wangerxian posted on 2022-8-1 16:06 FPGA's inout is indeed not easy to understand. IIC's SDA is in this mode.

Yes, I was a little confused at the beginning and didn’t know how to write simulation files.

。

wangerxian

1nnocent posted on 2022-8-1 16:47 Yes, I was a little confused at the beginning and didn’t know how to write the simulation file.

Yeah, but FPGAs are awesome!

xiaosong06

I have learned a lot, the explanation is very detailed, thank you

fengye2009

This introduction is quite detailed and useful. FPGA is developing rapidly now, and the summary here is very good and has reference value.

Fred_1977

I have come to this point now, but I still don’t know how to write simulation files. I am still learning.

wwens

Enable control in or out

LauPngChg

I came here to learn. Although I don’t understand, I can feel that the author of the post is very talented.

Fred_1977

I am still learning. At the beginning, I didn’t understand how to write simulation files. Now I understand a little bit and can write a little, but I am not proficient yet. I will continue to learn!

qsmax

Thanks for sharing

hkghf

The examples are good, you can learn from them. To learn FPGA, you still need to read more, practice more, and practice more. . . . .

xwd_bp

Learning, thank you