Verilog HDL design and practice

"Verilog HDL Design and Practice" is divided into four parts: basic operations of the ModelSim simulation tool and QuartusⅡ development tool, Verilog HDL syntax introduction, FPGA example design and NiosⅡ example design based on Qsys. First, the basic operations of QuartusII are introduced, including project creation, code editing, schematic design, VerilogHDL code design, waveform simulation based on QuartusII and ModelSim, and downloading of FPGA configuration files and other basic operations related to FPGA design. Then, the basic syntax of VerilogHDL is introduced one by one in the form of VerilogHDL knowledge points with VerilogHDL program examples. Then, using examples as the starting point, from simple to complex, the modeling of combinational circuits, sequential circuit modeling and the design of comprehensive examples are introduced.

• Chapter 1：Basic operations of ModelSim simulation tool and Quartus II development tool (31 minutes and 16 seconds)

• Chapter 2：A brief introduction to Verilog HDL (19 minutes and 35 seconds)

• Chapter 3：Verilog HDL data objects (12 minutes and 47 seconds)

• Chapter 4：Verilog HDL operators (22 minutes and 32 seconds)

• Chapter 5：Verilog HDL parallel statements (25 minutes and 8 seconds)

• Chapter 6：Verilog HDL sequential statements (11 minutes and 35 seconds)

• Chapter 7：Custom Primitives (UDP) for Verilog HDL (11 minutes and 10 seconds)

• Chapter 8：Verilog HDL tasks and functions (13 minutes and 27 seconds)

• Chapter 9：Other syntax knowledge of Verilog HDL (15 minutes and 45 seconds)

• Chapter 10：Verilog HDL test platform writing (7 minutes and 51 seconds)

• Chapter 11：Verilog HDL Design Specification (15 minutes and 1 seconds)

• Chapter 12：Verilog HDL basic combinational circuit modeling (13 minutes and 3 seconds)

• Chapter 13：Basic sequential circuit modeling in Verilog HDL (10 minutes and 21 seconds)

• Chapter 14：Channel encryption and decryption (4 minutes and 40 seconds)

• Chapter 15：CRC encoding (9 minutes and 2 seconds)

• Chapter 16：digital clock design (19 minutes and 20 seconds)

• Chapter 17：HDB3 encoding and decoding (26 minutes and 50 seconds)

• Chapter 18：SPI data communication (18 minutes and 34 seconds)

• Chapter 19：UART data communication (10 minutes and 48 seconds)

• Chapter 20：Traffic light controller modeling (5 minutes and 50 seconds)

• Chapter 21：The first Nios II system based on Qsys (21 minutes and 15 seconds)

• Chapter 22：PIO core application system (47 minutes and 21 seconds)

• Chapter 23：Application of UART core (31 minutes and 20 seconds)

• Chapter 24：Application of Interval Timer core (32 minutes and 19 seconds)

• Chapter 25：Application of SPI core (22 minutes and 0 seconds)

• Chapter 26：Custom peripherals and instructions based on Qsys (21 minutes and 12 seconds)