Verilog HDL hardware description language advanced training

The composition of digital systems in FPGA and key points of combinatorial logic design
Key points of sequential logic design
Types and uses of modules
Why Verilog can support
Verilog modules for large-scale design of RAM and stimulus sources How to call RAM top-level test Verilog modules
in Quartus II Composition and combination of digital logic circuits Logic example (1):: 8-bit data path controller Combinational logic example (2): An 8-bit three-state data path controller Switch logic application examples and delay issues Why should static random access memory (SRAM) design a finite state machine (1 ) Finite state machine representation method Global clock king and balanced tree structure Avoid risky competition and pipeline Example 1: Use gate-level structure to describe D flip-flop; Example 2: Write test module to check whether the design is correct through simulation; Example 3: Designed by modules to form a higher-level module; Example 4: D flip-flop with asynchronous reset terminal. Example: Implementation and testing of T flip-flops and counters Example: Design of a 4-bit full adder and instruction decoding circuit using a one-bit full adder Example: Testing of the instruction decoding circuit HDL models at different abstraction levels in FPGA design: System Level, algorithm level, register transfer level, gate level, switch level Key points of sequential logic design Top-level testing Verilog module in FPGA design

• Chapter 1：The composition of digital systems in FPGA and key points of combinatorial logic design (27 minutes and 18 seconds)

• Chapter 2：Key points of sequential logic design (13 minutes and 47 seconds)

• Chapter 3：Types and uses of modules (14 minutes and 48 seconds)

• Chapter 4：Why Verilog can support large designs (13 minutes and 5 seconds)

• Chapter 5：Verilog modules for RAM and stimulus sources (9 minutes and 37 seconds)

• Chapter 6：How to access RAM in Quartus II (10 minutes and 15 seconds)

• Chapter 7：Top-level test Verilog module (9 minutes and 1 seconds)

• Chapter 8：The composition of digital logic circuits (13 minutes and 20 seconds)

• Chapter 9：Combinational logic example (1):: 8-bit data path controller (14 minutes and 19 seconds)

• Chapter 10：Combinational logic example (2): an 8-bit three-state data path controller (9 minutes and 56 seconds)

• Chapter 11：Switch logic application examples and delay issues (6 minutes and 35 seconds)

• Chapter 12：Static Random Access Memory (SRAM) (3 minutes and 8 seconds)

• Chapter 13：Why design a finite state machine (1) (19 minutes and 10 seconds)

• Chapter 14：Finite state machine representation method (26 minutes and 28 seconds)

• Chapter 15：Global Clock King and Balanced Tree Structure (5 minutes and 8 seconds)

• Chapter 16：Avoid risky competition and assembly lines (7 minutes and 11 seconds)

• Chapter 17：Example: Use gate-level structure to describe D flip-flop (20 minutes and 51 seconds)

• Chapter 18：Example: Implementation and testing of T flip-flop and counter (9 minutes and 18 seconds)

• Chapter 19：Example: Design of a 4-bit full adder and instruction decoding circuit using a one-bit full adder (18 minutes and 38 seconds)

• Chapter 20：Example: Test of instruction decoding circuit (38 minutes and 5 seconds)

• Chapter 21：HDL models at different abstraction levels in FPGA design (7 minutes and 38 seconds)

• Chapter 22：Key points of sequential logic design (13 minutes and 26 seconds)

• Chapter 23：Top-level test Verilog module in FPGA design (2 minutes and 12 seconds)