IC Design and Methods

Integrated circuits are one of the essential components of modern electronic systems. The design process of digital integrated circuits includes front-end design and back-end design. In the front-end design stage, on the basis of completing the digital system architecture and algorithm design, the main design is Register Transfer Level (RTL) code, and logic synthesis generates a gate-level netlist; the back-end design includes layout planning, standards Brick unit placement and routing, layout generation and inspection, etc.
This course introduces the IC design process and design methods, basic knowledge of VHDL and Verilog languages, simulation tools, basic concepts of synthesis and tool usage.

• Chapter 1：Software download instructions (5 minutes and 14 seconds)

• Chapter 2：Integrated circuit applications and markets (9 minutes and 26 seconds)

• Chapter 3：Integrated circuit manufacturing process (11 minutes and 41 seconds)

• Chapter 4：Looking at the progress of IC from the perspective of CPU development (6 minutes and 29 seconds)

• Chapter 5：Looking at the progress of IC from the perspective of industry development (16 minutes and 34 seconds)

• Chapter 6：Looking at the development direction of IC from ISSCC (6 minutes and 14 seconds)

• Chapter 7：Implementation methods of digital systems (comparison of ASSP_FPGA_ASIC) (20 minutes and 33 seconds)

• Chapter 8：combinational logic circuit (12 minutes and 34 seconds)

• Chapter 9：Sequential logic circuit(1) (21 minutes and 42 seconds)

• Chapter 10：Sequential logic circuit(2) (16 minutes and 44 seconds)

• Chapter 11：Verilog history and learning points (7 minutes and 19 seconds)

• Chapter 12：Ports, signals and data types (16 minutes and 49 seconds)

• Chapter 13：Logic levels and data operations (7 minutes and 51 seconds)

• Chapter 14：Assign statement (14 minutes and 13 seconds)

• Chapter 15：Assign example (13 minutes and 25 seconds)

• Chapter 16：Always (16 minutes and 33 seconds)

• Chapter 17：Blocking and non-blocking assignment (26 minutes and 3 seconds)

• Chapter 18：Description of D flip-flop (11 minutes and 56 seconds)

• Chapter 19：Design of sequential circuits (26 minutes and 31 seconds)

• Chapter 20：Verilog syntax for testing (1) (16 minutes and 19 seconds)

• Chapter 21：Test-oriented Verilog syntax (2) (21 minutes and 28 seconds)

• Chapter 22：Circuit design example 1 (16 minutes and 59 seconds)

• Chapter 23：Circuit design example 2 (35 minutes and 39 seconds)

• Chapter 24：Modelsim simulation (26 minutes and 39 seconds)