Based on the requirements and characteristics of digital integrated circuit system engineering development, this book uses Verilog HDL to model, design and verify digital systems, and provides an in-depth explanation of the key technologies and processes of ASIC/FPGA system chip engineering design and development. The content includes: integrated circuit chip system modeling, circuit structure trade-offs, pipeline technology, multi-core microprocessors, functional verification, timing analysis, test platforms, fault simulation, testability design, logic synthesis, post-synthesis verification, and other key technologies and design cases in the front-end and back-end engineering design and implementation of integrated circuit systems. The book describes the principles, basic methods, practical technologies, design experience and skills that must be followed in the development of integrated circuit system engineering with a large number of design examples.
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