Design and simulation of FIR digital filter based on VerilogHDL

       introduction

      Digital filter is a basic processing component in applications such as speech and image processing, pattern recognition, radar signal processing, and spectrum analysis. It can meet the strict requirements of the filter on amplitude and phase characteristics and avoid problems such as voltage drift, temperature drift, and noise that analog filters cannot overcome.

     Finite impulse response (FIR) filters can be designed with arbitrary amplitude-frequency characteristics while ensuring strict linear phase characteristics.

　　1. FIR digital filter

　　A FIR filter forms its output as a weighted sum of current and past input samples, as described by the feed-forward difference equation shown below.

       FIR filter is also called moving average filter, because the output at any time point depends on a window containing the latest M input samples. Since its response depends only on a finite number of inputs, FIR filter has a finite length non-zero response to a discrete event impulse, that is, the response of an M-order FIR filter to an impulse is zero after M clock cycles.

　　The FIR filter can be described by the z-domain block diagram shown in Figure 1.

      Each box labeled z-1 represents a register cell with a one clock cycle delay. The diagram shows the data path and the operations that must be performed by the filter. Each filter stage stores a delayed input sample. The input and output connections of each stage are called taps, and the set of coefficients {hk} is called the filter tap coefficients. An M-order filter has M+1 taps. The data stream sample at each clock edge n (time subscript) is multiplied by the taps through the shift register and summed to produce the output yFIR[n]. The filter additions and multiplications must be fast enough to form y[n] before the next clock arrives. And they must be scaled in each stage to fit the width of their data path. In practical applications where precision is required, the lattice structure can reduce the impact of finite word length, but at an increased computational cost. The general goal is to filter as fast as possible to achieve a high sampling rate. The longest signal path through the combinational logic consists of M additions and one multiplication operation. The FIR structure specifies the finite word length of each arithmetic unit of the machine and manages the data flow during the operation.

　　2. Implementation of FIR digital filter design

　　There are currently three ways to implement FIR filters: using a monolithic general-purpose digital filter integrated circuit, DSP devices, and programmable logic devices. Monolithic general-purpose digital filters are easy to use, but due to the small specifications of word length and order, they cannot fully meet actual needs. Although it is simple to implement using DSP devices, the execution speed is bound to be slow due to the sequential execution of the program. FPGA/CPLD has a regular internal logic array and rich connection resources, which is particularly suitable for digital signal processing tasks. Compared with general-purpose DSP chips dominated by serial operations, it has better parallelism and scalability. However, for a long time, FPGA/CPLD has been used in system logic or timing control, and there are few applications in signal processing. The main reason is that there is a lack of effective structures for implementing multiplication operations in FPGA/CPLD.

　　Today's FPGA products are fully capable of this task. Altera's Stratix series products use a 1.5V core and are manufactured using a 0.13um all-copper process. In addition to all the features of previous Altera FPGA chips, they also have the following features: There are three types of RAM blocks in the chip, namely, a small RAM with a capacity of 512bit (M512), a standard RAM with a capacity of 4KB (M4K), and a large RAM with a capacity of 512KB (MegaRAM). The built-in hardware multiplier and DSP block with a multiplication-addition structure are suitable for high-speed signal processing; a new wiring structure is used, which is divided into three lengths of row and column wiring, which increases the flexibility of wiring while ensuring predictable delays; the on-chip terminal matching resistor is increased to improve signal integrity and simplify PCB wiring; and it also has clock management and phase-locked loop capabilities.

　　Verilog HDL Design Example of FIR Filter

　　1. Design Intent

　　This example focuses on implementing a basic finite impulse response filter in a Stratix device.

　　The basic structure of FIR consists of a series of multiplications and additions. The operation of FIR can be described by equation (1), which can be rewritten as follows:

        An L=8 FIR design is shown in Figure 2, which uses 8 samples of the input. Therefore, it is called an 8-tap filter. The structure consists of a shift register, a multiplier and an adder, which can realize an L=8 order FIR. Its data channel must be wide enough to accommodate the outputs of the multiplier and adder. These sample values ​​are encoded in a finite word length form and then moved in parallel through M registers. It can be seen that such a machine can be constructed using a MAC cascade chain. Each register provides a unit sample delay. These delayed inputs are multiplied by their respective coefficients and then superimposed to obtain the output. Figure 2 shows the structure of an 8th order FIR digital filter based on MAC [page]

        There are eight taps in this design, each with an 18-bit input and filter coefficients. Since one DSP block can support four branches with 18-bit inputs, the design requires two DSP blocks. The input data is loaded serially into the DSP block, and the shift-in/shift-out register chain inside the DSP is used to generate delays. The filter coefficients are loaded from the ROM memory of the TriMatrix?. [page]

        2. Verilog HDL code writing style

　　HDL code should be easy to read and reuse, and the top-down segmentation method can help us achieve the best results. HDL code should be as concise as possible while achieving the function, and try to avoid using instances with special library units, as this will make the whole process unreliable.

　　In this design, we divided the design into a top-level file and three sub-files, and called the MegaFunction function in QuartusII to assist in completing the entire design.

Figure 3 shows a top-level block diagram of a FIR filter.

Table 1: Port list of the FIR filter design example

       3. Verification simulation

　   One advantage of a fully synthesizable design is that the same HDL code can be used for verification and synthesis. Before using the HDL code, you must verify the functionality of the design. The best and easiest way is to use a verification tool, followed by a simulation tool for targeted simulation.

　　Quartus II has an internal simulator, and you can start simulating by creating a correct Vector Waveform File. Figure 4 shows the pulse response waveform of an 8th-order FIR obtained by the Quartus II internal simulator.

　　V. Conclusion

　　The biggest advantage of using Verilog HDL to design digital filters is that it makes the design more flexible. Compared with hardware circuit diagram design, the parameters designed in Verilog HDL language can be easily changed in the Verilog program. The circuit diagram can be obtained through simplification and synthesis of the synthesis tool, which is much more efficient than manual design using Karnaugh maps. Moreover, the compilation process is also very simple and efficient. Excellent coding style can save the units used by the chip during the synthesis process, thereby reducing the design cost.

　　References:

　　[1]. Xia Yuwen. VerilogHDL Digital System Design Tutorial, Beijing University of Aeronautics and Astronautics Press, Beijing. 2003.

　　[2]. Altera Corporation. Introduction to QuartusII. 2003

　　[3]. Michael D. Ciletti. Advanced Digital Design with Verilog HDL. Prentice Hall, NJ.2005.

　　[4]. Peng Bao et al. FPGA design based on Verilog HDL. Microcomputer Information, Vol. 20, No. 10, 2004