Location:Training / Embedded Development / MCU / SOC system-level chip design experiment / Verilog Delay

SoC Design Laboratory

Course Overview:
This course is designed to equip participants with the skills and knowledge required to become full-stack IC designers, capable of handling all development stages from front-end design to system debugging and embedded programming. After completing the course, participants will have the skills and knowledge to design SoC chips from concept to production, and achieve the following learning objectives:
1. Learn Verilog and HLS design implementation on FPGA and ASIC;
2. Implement IP and integrate it into SoC design;
3. Implement SoC design and verify it in FPGA;

This course is based on Google Open-Source Silicon Program, and the experiment uses Efabless Caravel Harness SoC. In this course, we will use Caravel SoC Harness and Caravel SoC FPGA verification platform.

Course Content:
Design Method
1. Introduction to HLS and Tools
2. Verilog & Logic Design
3. Caravel SoC
4. Processor
5. Memory
6. Peripheral
7. Embedded Programming
8. SoC - Interconnect
9. Static Timing Analysis
10. Synthesis & Optimization
11. Verification & Simulation

Design Process Tools
1. Tools – Tcl, Perl, Makefile
2. FPGA Flow -Xilinx Vivado
3. Simulator
4. Synthesis
5. Timing Analysis
6. Verification MethodologyExperiment

1.
Vivado Tool Installation
2. HLS - FIR Filter (AXI Master, AXI Stream)
3. Caravel SoC Simulation
4. Caravel SoC FPGA
5. SoC Design Labs: Interrupt, User RAM, UART, SDRAM
6. Workload Optimized SoC (WLOS) Baseline
7. Final Project