SOC system-level chip design experiment

SoC Design Laboratory

Course Overview:
This course is designed to equip participants with the skills and knowledge required to become full-stack IC designers, capable of handling all development stages from front-end design to system debugging and embedded programming. After completing the course, participants will have the skills and knowledge to design SoC chips from concept to production, and achieve the following learning objectives:
1. Learn Verilog and HLS design implementation on FPGA and ASIC;
2. Implement IP and integrate it into SoC design;
3. Implement SoC design and verify it in FPGA;

This course is based on Google Open-Source Silicon Program, and the experiment uses Efabless Caravel Harness SoC. In this course, we will use Caravel SoC Harness and Caravel SoC FPGA verification platform.

Course Content:
Design Method
1. Introduction to HLS and Tools
2. Verilog & Logic Design
3. Caravel SoC
4. Processor
5. Memory
6. Peripheral
7. Embedded Programming
8. SoC - Interconnect
9. Static Timing Analysis
10. Synthesis & Optimization
11. Verification & Simulation

Design Process Tools
1. Tools – Tcl, Perl, Makefile
2. FPGA Flow -Xilinx Vivado
3. Simulator
4. Synthesis
5. Timing Analysis
6. Verification MethodologyExperiment

1.
Vivado Tool Installation
2. HLS - FIR Filter (AXI Master, AXI Stream)
3. Caravel SoC Simulation
4. Caravel SoC FPGA
5. SoC Design Labs: Interrupt, User RAM, UART, SDRAM
6. Workload Optimized SoC (WLOS) Baseline
7. Final Project

• Chapter 1：Course plan (3 hours and 19 seconds)

• Chapter 2：HLS (2 hours and 59 minutes and 18 seconds)

• Chapter 3：Verilog (3 hours and 15 minutes and 29 seconds)

• Chapter 4：Lab3 Workbook Explained (45 minutes and 33 seconds)

• Chapter 5：Verilog Delay (26 minutes and 0 seconds)

• Chapter 6：Verilog FSM (22 minutes and 0 seconds)

• Chapter 7：Lab3 Instruction (25 minutes and 38 seconds)

• Chapter 8：SoC Introduction (27 minutes and 7 seconds)

• Chapter 9：Caravel SoC Introduction (6 minutes and 16 seconds)

• Chapter 10：Lab4-0 Introduction (4 minutes and 16 seconds)

• Chapter 11：Single Cycle Processor (1 hours and 8 minutes and 41 seconds)

• Chapter 12：Multi-Cycle Processor (58 minutes and 46 seconds)

• Chapter 13：Processor-SuperScalar (1 hours and 4 minutes and 36 seconds)

• Chapter 14：Lab4 Introduction (22 minutes and 20 seconds)

• Chapter 15：Lab3 Design Structure (49 minutes and 27 seconds)

• Chapter 16：Peripheral Interface Design (25 minutes and 50 seconds)

• Chapter 17：Peripheral Serial Bus (32 minutes and 25 seconds)

• Chapter 18：Timer, DMA (36 minutes and 22 seconds)

• Chapter 19：Design Interrupt (53 minutes and 4 seconds)

• Chapter 20：GPIO (41 minutes and 27 seconds)

• Chapter 21：Lab6 Explanation (17 minutes and 34 seconds)

• Chapter 22：LabD SDRAM Explanation (16 minutes and 9 seconds)

• Chapter 23：Lab4-2 Performance Optimization (31 minutes and 18 seconds)