Hardware Design of Vehicle-mounted GPS/DR Integrated Navigation System Based on DSP

summary

Aiming at the need of low-cost integrated navigation technology development and combining the characteristics of main sensors, this paper introduces the design of GPS/DR integrated navigation system which uses floating-point DSP TMS320VC33 as the core processor for integrated navigation algorithm implementation and TL16C554 for communication port expansion, and gives the design method of system hardware. The designed system has the characteristics of small size, low cost, good real-time performance, high reliability, good scalability, etc., and has wide application value.

1 Introduction

At present, the horizontal positioning accuracy of differential GPS has reached 3~5m, which fully meets the requirements of vehicle positioning accuracy. However, due to the problem of GPS signal obstruction in urban high-rise buildings or when crossing overpasses, GPS cannot be positioned normally. Dead reckoning (DR) is a commonly used vehicle positioning technology, but the direction sensor accumulates large errors over time and cannot be used alone for a long time. The use of an integrated navigation system can use the position and speed information provided by the GPS system to correct and compensate the errors of the DR system in real time; when the GPS signal is lost, the DR system can be used to complete dead reckoning, which improves the reliability of the integrated navigation system.

In addition to completing a large amount of computing and processing work, the integrated navigation system also needs to realize data collection of sensors such as inertial measurement unit IMU (gyroscope and accelerometer) and GPS, communication with external systems, timing logic control and human-machine interface. In this case, if only one DSP chip is used, the real-time performance of the system is poor, so most integrated systems use two or more DSPs or a master-slave multi-processor system composed of one or several general-purpose microprocessors MPU plus a DSP. At present, the solution of combining DSP and FPGA to process high-speed digital signals is becoming more and more widely used.

2 GPS/DR integrated navigation system composition

The GPS/DR combined system has the function of receiving and processing odometer information, electronic compass information, inertial measurement unit IMU and GPS information. The main block diagram of the system composition is shown in Figure 1.

Figure 1 Block diagram of the integrated navigation system

The absolute position information provided by GPS can provide DR with the initial value of the estimated positioning and perform error correction; on the other hand, the estimated results of DR can be used to compensate for some random errors in GPS positioning, thereby smoothing the positioning trajectory. Therefore, by combining the two systems using appropriate methods and making full use of the complementarity of their positioning information, it is possible to obtain higher positioning accuracy and reliability than using either method alone.

Central processing unit components

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At present, the navigation system has developed into a combined navigation system that uses multi-sensor data fusion. The navigation computer not only completes complex calculations, but also performs a large amount of data communication. Therefore, it must have a rich communication interface to complete the task of collecting and transmitting sensor data. This requires the central processing unit to be able to communicate with the outside world while ensuring calculation accuracy and speed.

Through functional analysis of the system, the navigation computer needs to complete data acquisition, data processing and data output functions. The data input part mainly completes the acquisition of various sensor output data; the data processing part mainly completes data filtering, error compensation and initial alignment of micro inertial measurement elements, Kalman filtering, and navigation parameter solution, etc.; the data output part is mainly responsible for the output of navigation parameters, which is used for positioning navigation or the input required for the next step. Due to the use of multiple sensors for information fusion, more peripheral communication interfaces are required. At the same time, the external sensor data output communication is mainly carried out through an asynchronous serial communication port that complies with the RS-232 standard. If it is directly connected to the central processing unit, a large number of interrupt responses will inevitably affect the CPU processing speed. At present, the serial port resources that various MCUs and MPUs can provide are also limited. Many traditional designs use PC104 as the central processor of the system. PC104 is large in size and high in price, which is not conducive to the miniaturization, low power consumption and low cost of the system. Therefore, this design considers the DSP+FPGA+TL16C554 solution, in which DSP completes the main navigation parameter calculation, uses TL16C554 to expand the external communication interface, and FPGA completes the serial port simulation and corresponding logic control to ensure high-speed communication between the three through the data line, thereby improving the system's operating efficiency and calculation accuracy.

The core processor of the central processing unit needs to complete large-scale matrix operations and algebraic operations, so the system uses the floating-point DSP chip TMS320VC33. The chip has an operating speed of 150MFLOPS and 75MIPS, and a single instruction cycle of 13ns. TMS320VC33 improves speed by improving hardware functions, while other processors improve speed by improving software functions or encoding rates. This way of improving performance through hardware is impossible on single-chip DSPs in the past. The processor has the powerful function of performing parallel multiplication arithmetic operations on integers and floating-point data simultaneously in a single cycle. At the same time, the chip has the characteristics of low power consumption and low cost, which meets the design requirements of the system.

FPGA has programmable characteristics and can easily complete the logic functions we need. FPGA is used to expand the peripheral communication interface, mainly to expand the TTL level serial communication port as a backup for the system. According to the resource requirements for completing serial communication and the consideration of future expansion, ACEX1K 30 (hereinafter referred to as ep1k30) of ALTERA is used here to complete this work. ep1k30 can provide 119,000 gate resources, with 1,728 logic macro units, can realize UART serial port, and can also complete corresponding decoding, logic control and other functions.

The system contains multiple sensors, which requires the processor to expand multiple serial ports. The DSP chip TMS320VC33 itself has a serial communication port. If the serial port resources on the DSP chip are directly used for serial communication, it is only suitable for occasions where the transmission data is relatively small and the transmission rate is slow. [ ] Its software programming is relatively complex, and controlling serial communication takes up a lot of system resources, affecting the real-time processing function of the sensor. Therefore, this system uses the 4-channel asynchronous transceiver integrated chip TL16C554 produced by TI to expand the DSP serial port and realize the communication between the sensor and the navigation computer. This chip is a large-scale integrated circuit chip with a serial asynchronous communication interface, which can realize the parallel/serial and serial/parallel conversion functions of data. It has a 16-byte FIFO buffer inside. In FIFO mode, the data is buffered as a 16-byte data packet before transmission and reception, reducing the number of CPU interrupts. It contains 4 improved 16C550 asynchronous transmission devices inside, making serial I/O more reliable.

The overall hardware design block diagram of the central processing unit is shown in Figure 2.

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The system makes full use of the advantages of DSP in addition and multiplication operations, realizes the real-time operation of navigation parameters, and uses FPGA and 16C554 to expand the peripheral communication interface, converts serial data into parallel data and communicates with DSP through the data bus, freeing the processor from the burden of a large number of I/O interrupt responses and improving the operating efficiency of the CPU. The solved navigation parameters are then transmitted to FPGA through the data bus and converted and output in the form of serial data. At the same time, considering that the amount of IMU data is large and the data update rate is greater than 100Hz, each packet of received data is not sent directly to the DSP, but first filtered and then temporarily stored through a FIFO. When the amount of data reaches a certain level, the DSP is notified to take the data away. This can further reduce the burden on the DSP and improve operating efficiency.

3 Hardware Design of Central Processing Unit

The hardware part of the central processing unit is mainly composed of power module, data communication module, FPGA part, DSP part, etc.

3.1 System power module

The whole system needs to use four voltages: 1.8V, 2.5V, 3.3V and 5V. Among them, DSP needs 1.8V and 3.3V as core power supply and I/O power supply; FPGA needs 2.5V and 3.3V voltage power supply; GPS needs 5V voltage power supply, so the whole system uses 5V voltage power supply. Then two TI TPS73HD3XX series chips are used for voltage conversion to obtain the required voltages respectively. TPS73HD3XX series chips are dual-channel voltage output conversion chips with very low quiescent current. Even for changing loads, the quiescent current can remain unchanged in practice.

3.2 Data Communication Module

The hardware structure diagram of the TL16C554 extended data communication module is shown in Figure 3.

The address lines A2~A0 and data lines D7~D0 of TL16C554 are directly connected to the address bus A2~A0 and external data lines D7~D0 of DSP respectively, while the chip select signals CSA~CSD, read/write signals IOR/IOW and interrupt signals INTA~INTD are connected to and processed by FPGA. Using FPGA in the circuit can flexibly configure the address of UART on the one hand, and flexibly generate the selection and read/write signals of UART on the other hand, thereby enhancing the flexibility of the system and facilitating system debugging.

3.3 FPGA part

Most traditional system designs are multi-machine parallel systems with DSP as the host responsible for data processing and single-chip microcomputer as the slave responsible for data acquisition. However, the speed limit of the slave single-chip microcontroller restricts the speed of the entire acquisition and processing system. In view of this situation, the traditional multi-machine structure is changed to a host-type single-machine structure: the system still uses DSP as the data processing host, and uses a pure hardware subsystem composed of various counters, logic circuits, and clock circuits to replace the previous slave system [4]. However, if the traditional method is adopted, that is, using standard digital circuit chips to expand and implement this subsystem, it is inevitable that multiple circuit chips are required, which not only makes the system structure complex and increases the number of connections, but also reduces reliability. Therefore, the system uses field programmable gate array devices FPGA to design this subsystem. The biggest advantage of using FPGA to design this system is that it saves PCB board area and meets the low cost requirements. And after the system design is completed, if you want to upgrade or improve the system, you don’t need to change any hardware circuits, you only need to reprogram the internal logic of the FPGA.

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The configuration information of FPGA cannot be saved after power failure, and it needs to be reconfigured when it is powered on again, so an off-chip memory is needed to save the configuration information. In this design, ALTERA's epc2 is selected as the configuration chip. epc2 is a programmable FLASH memory that can be erased and written multiple times, specifically used for the configuration of ALTERA's FPGA. At the same time, the JTAG port on the system board can realize the programming of epc2 and the online configuration of FPGA. The switching of online configuration of FPGA and programming of epc2 is realized by the dip switch. The specific hardware connection is shown in Figure 4.

3.4 DSP part

DSP requires system algorithm program memory, which is stored in FLASH memory. This system uses four 256k×16b CY7C1041 chips to expand two 256k×32b RAMs to provide storage space for complex combination algorithms; two 16-bit SST39VF400 FLASH chips are selected as the system program memory. The use of FLASH memory overcomes the disadvantage of the large size of traditional EPROM and helps to reduce the area of ​​the circuit board. Through the DSP emulator, the program can be written into FLASH according to the FLASH burning algorithm to complete the storage of the DSP algorithm. When the system is powered on, the program can be loaded quickly through the bootstrap method. This can reduce the cost, size and power consumption of the system.

Add a FIFO before the DSP, and wait for the data to meet the requirements before reading it together with the DSP, thereby solving the problem of frequent CPU response caused by the large amount of IMU output data. Optimize the efficiency of the system. Each data in the IMU data consists of two parts, the high byte and the low byte. After receiving the data through the serial port, it can be merged into a 16-bit form. The 16C554 chip has a 16-byte FIFO buffer, which meets the requirements of the system. The half-full signal of the FIFO is used as an interrupt signal to notify the DSP to receive data and notify the DSP to read. According to the overhead time of DSP reading and writing data and the amount of calculation performed, and considering the size of the actual received data and the transmission baud rate, calculate the time it takes for the DSP to process a packet of data and the time it takes to write a packet of data in the FIFO, so that the system can successfully complete the solution task.

4 Conclusion

The GPS/DR vehicle combined positioning and navigation system combines the GPS system with the DR system to improve the effectiveness, integrity and accuracy of the system. The DR dead reckoning system can ensure the output of vehicle position information when the satellite signal is lost. The system has the characteristics of all-round, all-weather, unobstructed and high-precision, and has good application prospects. This combined navigation system has powerful data processing capabilities, and has the advantages of small size, low cost, high reliability and good real-time performance. This design gives full play to the powerful data processing capabilities of DSP, and utilizes the advantages of FPGA's high integration, convenient programming and simulation, and fast speed. It also makes the system have great room for improvement in the future, and can achieve different functions with the same hardware.