​Simple Steps to Calculate Sample Clock Jitter for Isolated Precision High-Speed ​​DAQ

Figure 15. Calculated maximum SNR for the ADAQ23875 and ADN4654.

Figure 16. Calculated maximum values ​​of ENOB for the ADAQ23875 and ADN4654.

in conclusion

Jitter in the signal (or clock) that controls the sample-and-hold switch in the ADC can affect the SNR performance of a precision high-speed DAQ signal chain. When selecting the components that make up the clock signal chain, it is important to understand the various error sources that contribute to the overall jitter.

When an application requires isolating a DAQ signal chain from a backplane, selecting a low additive jitter digital isolator is key to maintaining excellent SNR performance. ADI offers low jitter LVDS isolators that help system designers achieve high SNR performance in isolated signal chain architectures.

The reference clock is the number one source of jitter in the sampling clock, so a low-jitter reference clock is required to achieve excellent performance in isolated high-speed DAQ. In addition, the signal integrity of the path between the FPGA and the reference clock must be ensured to avoid additional errors introduced by the path itself.

Acknowledgements

The authors would like to thank Michael Hennessy and Stuart Servis for their technical contributions to this article.

References

B.E. Boser and B.A. Wooley. “Design of a Sigma-Delta Modulated Analog-to-Digital Converter.” IEEE Journal of Solid-State Circuits, Vol. 23, No. 6, December 1988.

Steven Harris. “Effects of Sampling Clock Jitter on Nyquist-Sampling Analog-to-Digital Converters and Oversampled Sigma-Delta ADCs.” Audio Engineering Society Journal, Vol. 38, No. 7/8, July/August 1990.

Kester, Walt. “MT-008 Tutorial: Converting Oscillator Phase Noise to Time Jitter.” Analog Devices, Inc., 2009.

Derek Redmayne, Eric Trelewicz, and Alison Smith. “Understanding the Effects of Clock Jitter on High Speed ​​ADCs.” Analog Devices, Inc., 2006.

About the Author

Lloben Paculanan is a product applications engineer at ADI Philippines GT. He joined ADI in 2000 and has held various test hardware development and applications engineering positions; he has been working on precision high-speed signal chain µModule development. He holds a bachelor’s degree in industrial engineering technology from Xavier University Ateneo de Cagayan College, and a bachelor’s degree in computer engineering from Enverga University. He can be contacted at lloben.paculanan@analog.com.

John Neeko Garlitos is a product applications engineer for signal chain μModule solutions at Analog Devices. He works on signal chain μModule development and embedded software for Circuits from the Lab and reference circuits. He started working at ADI Philippines GT in 2017. He holds a Bachelor of Science degree in electronic engineering from the Technological University of the Philippines-Sayan and a Master of Science degree in electronic engineering from the University of the Philippines-Diliman. Contact him at johnneeko.garlitos@analog.com.