Detailed explanation of S3C2440 clock system

Before talking about the system clock, because these devices are all dependent on the system clock, we must first talk about the system clock. The clock system of S3C2440 is as follows

There are two types of external clock sources, crystal oscillator or external frequency, which are selected by om3-2. The clock circuit also has two types according to the two choices.

We can draw the following conclusions by analyzing the clock diagram: The selected external clock enters MPLL and is multiplied by the phase-locked loop. After passing through the phase-locked loop, the clock MPLL_IN is divided into three parts, namely FCLK, HCLK, and PCLK. Among them, HCLK and PCLK are obtained by dividing the HCLK. Finally, the ARM920T system kernel module obtains two clocks, HCLK and FCLK. The DMA controller, LCD controller, memory controller, bus controller, external nand controller and TIC, and the camera interface all come from the HCLK clock. The LCD controller, nand controller, and cam camera controller clocks can be selected to be cut off from the bus, IIC WDT IIS PWM SDI GPIO ADC RTC UART012 SPI These AC97 peripherals are all connected to the PCLK bus, and except for WDT, they can be disconnected from the bus. In addition, the USB clock is directly obtained from the MPLL_IN multiplier to generate UCLK. The USB host clock can choose UCLK or HCLK, and the USB device clock can choose UCLK or PCLK. Therefore, sometimes it is a good choice to look at the picture when you first come into contact with the chip. The text is more detailed, and looking at the picture can quickly browse the whole picture. Through our analysis, we can get the following simplified document

This is the basic distribution of the system clock. The remaining details are nothing more than how to divide the frequency, how to enable the clock and stop the clock, the phase-locked loop configuration, etc. First, focus on MPLL

This is the PLL lock time. Generally, you can set it smaller to check whether the lock is successful.

These three values ​​can be combined to select different MCLKs. There is a formula in the data sheet. After MPLL multiplication, the system master clock FCLK (that is, the ARM920T clock) is successfully obtained.

Use this register to enable and cut off the clock. Don't forget this register when using peripherals.

This register determines the ratio at which FCLK is divided into HCLK and PCLK.

At this point, we have basically described the system clock. As long as we understand the framework, the clock is actually quite simple, the frequency division coefficient, power control, and the most important thing is to understand which device uses which clock.

Next, we will show you a code to calculate the system clock (the process of setting the clock can be found in 2440init.s, which you can refer to)

Clock.c

#include "clock.h"

#define FIN (12000000)	

U32 FCLK;
U32 HCLK;
U32 PCLK;
U32 UCLK;


void CalcBusClk(void) //Calculate bus frequency
{
	U32 val,UPLL;
	U8 m, p, s;
	val = rMPLLCON;
	m = (val >> 12) & 0xff;
	p = (val >> 4) & 0x3f;
	s = val & 3;

	FCLK = ((m+8)*(FIN/100)*2)/((p+2)*(1<> 1) & 3;
	p = val & 1;	
	val = rCAMDIVN;
	s = val >> 8;
	
	switch (m) 
	{
		case 0:
			HCLK = FCLK;
			break;
		case 1:
			HCLK = FCLK >> 1;
			break;
		case 2:
			if(s & 2)
				HCLK = FCLK >> 3;
			else
				HCLK = FCLK >> 2;
			break;
		case 3:
			if(s & 1)
				HCLK = FCLK / 6;
			else
				HCLK = FCLK / 3;
			break;
	}
	
	if(p)
		PCLK = HCLK >> 1;
	else
		PCLK = HCLK;
		
	val = rUPLLCON;
	m = (val >> 12) & 0xff;
	p = (val >> 4) & 0x3f;
	s = val & 3;
	UPLL = ((m+8)*FIN)/((p+2)*(1<>1):UPLL;
}

//************************[HCLK, PCLK]************************ **********
void ChangeClockDivider(int hdivn_val,int pdivn_val)
{
	int hdivn=2, pdivn=0;
	
	// hdivn_val (FCLK:HCLK)ratio hdivn
	// 11 1:1 (0)
	// 12 1:2 (1)
	// 13 1:3 (3) 
	// 14 1:4 (2)
	// pdivn_val (HCLK:PCLK)ratio pdivn
	// 11 1:1 (0)
	// 12 1:2 (1)
	switch(hdivn_val) {
		case 11: hdivn=0; break;
		case 12: hdivn=1; break;
		case 13:
		case 16: hdivn=3; break;
		case 14: 
		case 18: hdivn=2; break;
	}
	
	switch(pdivn_val) {
		case 11: pdivn=0; break;
		case 12: pdivn=1; break;
	}
	
	rCLKDIVN = (hdivn<<1) | pdivn;

	switch(hdivn_val) {
		case 16: // when 1, HCLK=FCLK/8.
			rCAMDIVN = (rCAMDIVN & ~(3<<8)) | (1<<8); 
		break; 
		case 18: // when 1, HCLK=FCLK/6.
			rCAMDIVN = (rCAMDIVN & ~(3<<8)) | (1<<9); 
		break;
	}
	
	if(hdivn!=0)
		MMU_SetAsyncBusMode();
	else 
		MMU_SetFastBusMode();
}



//******************************[UPLL]********************** ************
void ChangeUPllValue(int mdiv,int pdiv,int sdiv)
{
	rUPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv;
}



//******************************[MPLL]****************** **********
void ChangeMPllValue(int mdiv,int pdiv,int sdiv)
{
	rMPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv;
}


//****************************Clock configuration function********************************
void SetClock(u8 mpll)
{
	if(mpll == MPLL271)
	{
		ChangeMPllValue(173,2,2);	
	}
	else if(mpll == MPLL304)
	{
		ChangeMPllValue(68,1,1);
	}
	else if(mpll == MPLL405)
	{
		ChangeMPllValue(127,2,1);
	}
	else if(mpll == MPLL532)
	{
		ChangeMPllValue(125,1,1);
	}
	ChangeClockDivider(14,12); //Set the division ratio to 1:4:8 fclk hclk pclk 
									//And set the CPU asynchronous bus mode
	CalcBusClk(); //Calculate bus frequency

	
}

Clock.h

#ifndef __CLOCK_H_
#define __CLOCK_H_
#include "def.h"
#include "2440addr.h"
#include "2440slib.h"

#define FIN (12000000) //External crystal
#define MPLL271 1 //Several typical clock macro definitions
#define MPLL304 2
#define MPLL405 3
#define MPLL532 4

void CalcBusClk(void); //Calculate bus frequency
void ChangeClockDivider(int hdivn_val,int pdivn_val); //Calculate the frequency division value
void ChangeUPllValue(int mdiv,int pdiv,int sdiv); //Configure USB bus
void ChangeMPllValue(int mdiv,int pdiv,int sdiv);
void SetClock(u8 mpll); //Configure system clock

extern U32 FCLK;
extern U32 HCLK;
extern U32 PCLK;
extern U32 UCLK;



#endif

Now that we have the specific numbers of several system clocks, we can configure the peripheral clocks well.

Note that when setting the system clock, if the HCLK is too large, the SDRAM value will not keep up. To solve this problem, Samsung has proposed such a solution, please pay attention to it: