Using VPX-based PCIe systems for asynchronous clocking

The VITA46 VPX standard defines a universal form factor chassis that can accommodate a variety of form factors (Reference 1). These cards plug into a universal backplane. This design uses PCIe VITA46.4 to transfer data between peripheral cards and the host controller in a VPX system. It uses PCIe Revision 1, which operates at 2.5Gbps. All VPX-compliant cards must use their own independent clock, which is different from other PCIe-compliant systems, such as PCs. VPX peripheral cards must also establish their own clock for PCIe transactions, which means that the clock is phase-independent from the host single-board computer. Therefore, the peripheral clock is asynchronous. The PCIe standard allows this, but has strict jitter tolerance requirements for all asynchronous PCIe clocks.

The peripheral card in this design uses an FPGA as the main digital processing device. Evaluation boards from FPGA vendors usually use PCIe interfaces, but asynchronous clocks are not used on the boards. To implement asynchronous clocks, a clock chip that is precisely matched to a certain type of oscillator crystal can be used (Figure 1). The clock chip IC has jitter, aging, and impedance requirements for the crystal. The crystal should meet these requirements within the temperature range of -40°C to +85°C. The crystal load capacitance value must be calculated using the formula in the CY24293 data sheet. The clock from the CY24293 is directly fed into the high-speed transceiver clock pin of the FPGA, resulting in reliable PCIe packet transmission between the peripheral card and the single-board computer. The CY24293 has some other component and layout requirements. It uses a PCIe device routing configuration that requires a special length of controlled impedance routing and a special value of series resistor.