Digital VLSI Design Tsinghua University Li Xiangyu

"Digital Large Scale Integrated Circuit" is a basic course for graduate students in microelectronics that teaches the basic theory and knowledge of digital large scale integrated circuits. It is not only a core course for students majoring in microelectronics, but also a basic course for students majoring in power supply to learn digital integrated circuit design. The course focuses on nanometer and deep submicron CMOS process conditions, digital circuit principles and design techniques at the system level integration level, including the characteristics and models of devices and interconnect lines, key indicators and optimization methods of digital VLSI, and common logic Type, basic functional units, working principles and design methods of important on-chip subsystems (clock, power network), etc. By studying this course, you can understand how to use MOS tubes to implement complex digital chips, what are the differences between real digital integrated circuits and ideal digital circuits, and the speed, power consumption, robustness, cost, etc. of the chip. What factors are related to the characteristics and how to optimize them.

• Chapter 1：The significance of integrated circuit technology (8 minutes and 36 seconds)

• Chapter 2：switches and logic (18 minutes and 20 seconds)

• Chapter 3：Static complementary CMOS logic principle (27 minutes and 18 seconds)

• Chapter 4：Design of static complementary CMOS logic gates and summary of this section (10 minutes and 19 seconds)

• Chapter 5：Integrated circuit technology (15 minutes and 15 seconds)

• Chapter 6：integrated circuit layout (11 minutes and 22 seconds)

• Chapter 7：Scaling Down (11 minutes and 55 seconds)

• Chapter 8：MOS tube principle (7 minutes and 29 seconds)

• Chapter 9：threshold voltage (16 minutes and 52 seconds)

• Chapter 10：Basic current equation of MOS tube (23 minutes and 28 seconds)

• Chapter 11：channel length modulation effect (3 minutes and 45 seconds)

• Chapter 12：speed saturation (26 minutes and 58 seconds)

• Chapter 13：Manual analysis model of MOS tube (7 minutes and 36 seconds)

• Chapter 14：Capacitance of MOS tube (23 minutes and 39 seconds)

• Chapter 15：body effect (6 minutes and 5 seconds)

• Chapter 16：Short channel effect, DIBL and summary of this section (11 minutes and 16 seconds)

• Chapter 17：subthreshold current (7 minutes and 12 seconds)

• Chapter 18：Gate oxide leakage current (3 minutes and 23 seconds)

• Chapter 19：Diffusion area pn junction leakage current (2 minutes and 40 seconds)

• Chapter 20：Gate-induced drain leakage and summary of this section (4 minutes and 34 seconds)

• Chapter 21：Temperature characteristics of MOS tubes (12 minutes and 7 seconds)

• Chapter 22：Voltage transfer characteristics (9 minutes and 29 seconds)

• Chapter 23：VTC analysis method (17 minutes and 15 seconds)

• Chapter 24：Switching threshold voltage and summary of this section (11 minutes and 4 seconds)

• Chapter 25：Single stage noise margin (22 minutes and 47 seconds)

• Chapter 26：Stability of voltage transfer characteristics (8 minutes and 31 seconds)

• Chapter 27：Multi-level noise tolerance and summary of this section (9 minutes and 44 seconds)

• Chapter 28：Static Characteristics of Complex Logic Gates (15 minutes and 18 seconds)

• Chapter 29：Inverter model for delay analysis (20 minutes and 47 seconds)

• Chapter 30：Inverter drive resistor (20 minutes and 56 seconds)

• Chapter 31：Inverter load capacitance (26 minutes and 36 seconds)

• Chapter 32：The composition of gate delay (2 minutes and 30 seconds)

• Chapter 33：Design Guidelines for Inverter Delay (18 minutes and 21 seconds)

• Chapter 34：Driving resistors for complex logic gates (17 minutes and 32 seconds)

• Chapter 35：Dimensional design of large fan-in logic gates (13 minutes and 55 seconds)

• Chapter 36：Delay model considering internal node capacitance (30 minutes and 44 seconds)

• Chapter 37：The relationship between complex logic gate delay and input pattern (12 minutes and 34 seconds)

• Chapter 38：Logic gate delay model (10 minutes and 35 seconds)

• Chapter 39：intrinsic delay (19 minutes and 19 seconds)

• Chapter 40：effort delay (40 minutes and 59 seconds)

• Chapter 41：Critical Path (13 minutes and 24 seconds)

• Chapter 42：Optimization of the size of logical paths when the number of levels is fixed (15 minutes and 24 seconds)

• Chapter 43：Optimization of the size of logical paths when the number of stages is variable (24 minutes and 40 seconds)

• Chapter 44：Summary of logical path size optimization methods (8 minutes and 48 seconds)

• Chapter 45：Circuit level optimization (14 minutes and 0 seconds)

• Chapter 46：Logical structure optimization (6 minutes and 0 seconds)

• Chapter 47：Chapter summary (6 minutes and 15 seconds)

• Chapter 48：Integrated circuit power consumption issues (8 minutes and 6 seconds)

• Chapter 49：Logic gate capacitor charging power consumption model (19 minutes and 26 seconds)

• Chapter 50：switch activity (17 minutes and 21 seconds)

• Chapter 51：false flip (8 minutes and 9 seconds)

• Chapter 52：Power dissipation caused by DC path and summary of this section (23 minutes and 39 seconds)

• Chapter 53：Static power consumption component of CMOS logic gates (12 minutes and 18 seconds)

• Chapter 54：Sub-threshold leakage current power consumption (5 minutes and 40 seconds)

• Chapter 55：stacking effect (18 minutes and 45 seconds)

• Chapter 56：Summary of this section (9 minutes and 52 seconds)

• Chapter 57：Power consumption optimization index (16 minutes and 7 seconds)

• Chapter 58：Supply voltage optimization (14 minutes and 37 seconds)

• Chapter 59：Joint optimization of VDD-dimensions (17 minutes and 18 seconds)

• Chapter 60：VDD-VT joint optimization (20 minutes and 47 seconds)

• Chapter 61：wires in integrated circuits (7 minutes and 59 seconds)

• Chapter 62：Parasitic capacitance of interconnect lines (7 minutes and 28 seconds)

• Chapter 63：Interconnect Parasitic Resistance (7 minutes and 27 seconds)

• Chapter 64：Summary of the influence and parasitic effects of inductance (6 minutes and 9 seconds)

• Chapter 65：Lumped Capacitance Model (7 minutes and 3 seconds)

• Chapter 66：distributed rc model (18 minutes and 44 seconds)

• Chapter 67：Circuit Delay Considering Interconnect Line Delay (7 minutes and 38 seconds)

• Chapter 68：Optimization of interconnect delay (24 minutes and 39 seconds)

• Chapter 69：Capacitive crosstalk and its effects (23 minutes and 4 seconds)

• Chapter 70：Methods to Overcome Capacitive Crosstalk (8 minutes and 12 seconds)

• Chapter 71：IR Drop (16 minutes and 15 seconds)

• Chapter 72：L(didt) (17 minutes and 42 seconds)

• Chapter 73：Summary of Signal Integrity of Interconnect Lines (6 minutes and 55 seconds)

• Chapter 74：Scaling Down of Interconnect Lines (14 minutes and 45 seconds)

• Chapter 75：combinational logic (3 minutes and 22 seconds)

• Chapter 76：Characteristics of static complementary CMOS logic (11 minutes and 32 seconds)

• Chapter 77：Static characteristics of pseudo-NMOS logic gates (18 minutes and 58 seconds)

• Chapter 78：Propagation delay of pseudo NMOS logic gate (16 minutes and 15 seconds)

• Chapter 79：Power consumption and characteristics of pseudo NMOS logic gates (6 minutes and 38 seconds)

• Chapter 80：Differential Series Voltage Switching Logic (23 minutes and 50 seconds)

• Chapter 81：How transfer tube logic works (29 minutes and 15 seconds)

• Chapter 82：Delay and power consumption of transmission tube logic (10 minutes and 10 seconds)

• Chapter 83：Level restoration technology (30 minutes and 35 seconds)

• Chapter 84：low threshold transfer tube (5 minutes and 47 seconds)

• Chapter 85：CMOS transmission gate (13 minutes and 14 seconds)

• Chapter 86：Integrity issues of transmission tube logic signals (18 minutes and 52 seconds)

• Chapter 87：dynamic logic (1 minutes and 32 seconds)

• Chapter 88：Basic principles of dynamic logic (15 minutes and 36 seconds)

• Chapter 89：Tandem dynamic doors (28 minutes and 42 seconds)

• Chapter 90：Dynamic logic speed (13 minutes and 10 seconds)

• Chapter 91：Dynamic logic power consumption (8 minutes and 29 seconds)

• Chapter 92：charge leakage (17 minutes and 35 seconds)

• Chapter 93：charge sharing (5 minutes and 45 seconds)

• Chapter 94：capacitive coupling (20 minutes and 37 seconds)

• Chapter 95：Choice of combinational logic type (14 minutes and 13 seconds)

• Chapter 96：Sequential logic and sequential units (10 minutes and 48 seconds)

• Chapter 97：bistable principle (7 minutes and 31 seconds)

• Chapter 98：Latches (13 minutes and 43 seconds)

• Chapter 99：Master-slave edge trigger register (12 minutes and 47 seconds)

• Chapter 100：Definition of timing parameters (23 minutes and 6 seconds)

• Chapter 101：The impact of timing parameters on synchronization systems (12 minutes and 18 seconds)

• Chapter 102：dynamic sequential unit (15 minutes and 17 seconds)

• Chapter 103：Chapter summary (3 minutes and 43 seconds)

• Chapter 104：Synchronization timing (15 minutes and 43 seconds)

• Chapter 105：clock system (9 minutes and 2 seconds)

• Chapter 106：clock skew (22 minutes and 36 seconds)

• Chapter 107：clock jitter (12 minutes and 41 seconds)

• Chapter 108：Sources of clock skew and jitter (22 minutes and 38 seconds)

• Chapter 109：Techniques to Reduce Clock Skew and Jitter (3 minutes and 13 seconds)

• Chapter 110：clock tree (12 minutes and 34 seconds)

• Chapter 111：Clock technology summary (6 minutes and 32 seconds)

• Chapter 112：Data path characteristics (8 minutes and 1 seconds)

• Chapter 113：Addition operations in digital circuits (21 minutes and 59 seconds)

• Chapter 114：Static complementary CMOS full adder (16 minutes and 34 seconds)

• Chapter 115：Static complementary CMOS full adder (13 minutes and 42 seconds)

• Chapter 116：Transmission tube logic full adder (8 minutes and 3 seconds)

• Chapter 117：dynamic logic full adder (10 minutes and 13 seconds)

• Chapter 118：carry select adder (24 minutes and 45 seconds)

• Chapter 119：carry lookahead adder (13 minutes and 9 seconds)

• Chapter 120：tree adder (30 minutes and 9 seconds)

• Chapter 121：Multiplication in digital circuits (15 minutes and 11 seconds)

• Chapter 122：partial product generation (25 minutes and 59 seconds)

• Chapter 123：Partial accumulation plus (16 minutes and 6 seconds)

• Chapter 124：Multiplier summary (9 minutes and 59 seconds)

• Chapter 125：chapter summary (5 minutes and 6 seconds)