​Simple Steps to Calculate Sample Clock Jitter for Isolated Precision High-Speed ​​DAQ

The Easy Steps to Calculate Sampling Clock Jitter for Isolated, Precision High Speed ​​DAQs

Simple Steps to Calculate Sample Clock Jitter for Isolated Precision High-Speed ​​DAQ

Introduction

Many data acquisition (DAQ) applications require isolation of DAQ signal chain paths for robustness, safety, high common-mode voltage considerations, or to eliminate ground loops that can introduce errors in measurements. ADI's precision, high-speed technology enables system designers to achieve high AC and DC accuracy in the same design without sacrificing DC accuracy for higher sampling rates. However, to achieve high AC performance, such as signal-to-noise ratio (SNR), system designers must consider the errors introduced by jitter on the sampling clock signal or the conversion start signal that controls the sample-and-hold (S&H) switch in the ADC. As the target signal and sampling rate increase, jitter on the signal that controls the sample-and-hold switch becomes a major error source.

When the DAQ signal chain is isolated, the signal that controls the sample-and-hold switch typically comes from the backplane where multiple channels are sampled simultaneously. It is critical that the system designer selects low jitter digital isolators so that the control signal to the sample-and-hold switch going to the ADC has low jitter. The LVDS interface format is the preferred format for precision, high speed ADCs to meet high data rate requirements. It also introduces minimal disturbance to the DAQ power and ground planes. This article will explain how to interpret the jitter specifications of Analog Devices’ LVDS digital isolators and which specifications are important when interfacing with precision, high speed products such as the ADAQ23875 DAQ µModule® solution. These guidelines also apply to other precision, high speed ADCs with LVDS interfaces. The methodology used to calculate the expected impact on SNR will also be explained when describing the ADAQ23875 used in conjunction with the ADN4654 Gigabit LVDS isolator.

How Jitter Affects the Sampling Process

Typically, a clock source has jitter in the time domain. When designing a DAQ system, it is important to understand how much jitter is contained in the clock source.

Figure 1 shows a typical output spectrum of a non-ideal oscillator, showing the noise power as a function of frequency in a 1 Hz bandwidth. Phase noise is defined as the ratio of the noise in a 1 Hz bandwidth at a specified frequency offset, fm, to the amplitude of the oscillator signal at the fundamental frequency, fo.

Figure 1. Oscillator power spectrum affected by phase noise.

The sampling process is the multiplication of the sampling clock and the analog input signal. This multiplication in the time domain is equivalent to convolution in the frequency domain. Therefore, during the ADC conversion, the spectrum of the ADC sampling clock is convolved with the pure sine wave input signal, so that the jitter on the sampling clock or phase noise appears in the FFT spectrum of the ADC output data, as shown in Figure 2.

Figure 2. Effect of sampling an ideal sine wave with phase noise on the sampling clock.

Isolated Precision High-Speed ​​DAQ Applications

A multiphase power analyzer is an example of an isolated precision high-speed DAQ application. Figure 3 shows a typical system architecture where channels are isolated from each other and a common backplane is used to communicate with the system computing or controller module. In this example, the ADAQ23875 precision high-speed DAQ solution was chosen because of its small size, which allows multiple isolated DAQ channels to be easily installed in a small space, thereby reducing the weight of mobile instruments in field test applications. LVDS Gigabit isolators (ADN4654) are used to isolate the DAQ channels from the main chassis backplane.

By isolating each DAQ channel, each channel can be directly connected to sensors with different common-mode voltages without damaging the input circuitry. The ground of each isolated DAQ channel tracks the common-mode voltage with a certain voltage offset. If the DAQ signal chain can track the common-mode voltage associated with the sensor, there is no need to use input signal conditioning circuits to support larger input common-mode voltages and eliminate the higher common-mode voltages to downstream circuits. This isolation also provides safety and eliminates ground loops that may affect measurement accuracy.

In power analyzer applications, it is critical to synchronize the sampling events across all DAQ channels, as mismatches in the time domain information associated with the sampled voltages can affect subsequent calculations and analysis. To synchronize the sampling events between channels, the ADC sampling clock is sent out of the backplane through an LVDS isolator.

In the isolated DAQ architecture shown in Figure 3, these jitter error sources contribute to the overall jitter on the sampling clock that controls the sample-and-hold switch in the ADC.

1. Reference clock jitter

The first source of sampling clock jitter is the reference clock. This reference clock is transmitted through the backplane to each isolated precision high-speed DAQ module and other measurement modules plugged into the backplane. This clock is used as the timing reference for the FPGA; therefore, the timing accuracy of all events, digital blocks, PLLs, etc. in the FPGA depends on the accuracy of the reference clock. In some applications where there is no backplane, an onboard clock oscillator is used as the reference clock source.

2. FPGA Jitter

The second source of sampling clock jitter is jitter introduced by the FPGA. Note that the FPGA contains a trigger-execution path, and the jitter specifications of the PLL and other data blocks in the FPGA will affect the overall jitter performance of the system.

3. LVDS isolator jitter

The third source of sampling clock jitter is the LVDS isolator. The LVDS isolator generates additional phase jitter, which affects the overall jitter performance of the system.

4. ADC Aperture Jitter

The fourth source of sampling clock jitter is the ADC's aperture jitter. This is inherent to the ADC and defined on the data sheet.

The fourth source of sampling clock jitter is the aperture jitter of the ADC. This is an inherent characteristic of the ADC itself, please refer to the data sheet for the specific definition.

Figure 3. Channel-to-channel, isolated DAQ architecture.

Figure 3. Channel-to-channel isolated DAQ architecture

There are reference clock and FPGA jitter specifications that are given in terms of phase noise. To calculate the jitter contribution to the sampling clock, the phase noise specification in the frequency domain needs to be converted to a jitter specification in the time domain.

Some reference clock and FPGA jitter specifications are given based on phase noise. To calculate the jitter contribution to the sampling clock, it is necessary to convert the phase noise specification in the frequency domain to a jitter specification in the time domain.

Calculating Jitter from Phase Noise

The phase noise curve is somewhat similar to the input voltage noise spectral density of an amplifier. As with amplifier voltage noise, it is best to use a low 1/f corner frequency in the oscillator. Oscillators are often described in terms of phase noise, but in order to relate phase noise to the performance of an ADC, the phase noise must be converted to jitter. To relate the plot in Figure 4 to modern ADC applications, an oscillator frequency of 100 MHz (sampling frequency) was chosen for ease of discussion and a typical curve is shown in Figure 4. Note that the phase noise curve is fitted by multiple line segments, with the endpoints of each segment defined by the data points.

Figure 4. Calculating jitter from phase noise.

The first step in calculating the equivalent rms jitter is to obtain the integrated phase noise power in the frequency range of interest, i.e., area A of the curve. The curve is divided into several independent areas (A1, A2, A3, and A4), each defined by two data points. Assuming no filtering between the oscillator and the ADC input, the upper limit of the integration frequency range should be twice the sampling frequency, which is approximately the bandwidth of the ADC sampling clock input. The choice of the lower limit of the integration frequency range also requires some consideration. In theory, it should be as low as possible to obtain the true rms jitter. In practice, however, manufacturers generally do not provide oscillator characteristics at offset frequencies less than 10 Hz, but this is enough to produce a sufficiently accurate result in the calculation. In most cases, if the characteristics at 100 Hz are provided, it is reasonable to choose 100 Hz as the lower limit of the integration frequency. Otherwise, 1 kHz or 10 kHz data points can be used. It should also be considered that close-in phase noise affects the spectral resolution of the system, while broadband noise affects the overall system signal-to-noise ratio. The most sensible approach is probably to integrate each area separately and examine the magnitude of the jitter contribution in each area. If a crystal oscillator is used, the low frequency contribution may be negligible compared to the broadband contribution. Other types of oscillators may have significant jitter contributions in the low frequency region, and their importance to the overall system frequency resolution must be determined. Integration in each region produces individual power ratios, which are then added and converted back to dBc. Knowing the integrated phase noise power, the rms phase jitter (in radians) can be calculated using the following equation: