Design of Network Camera Based on TMS320DM642

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Design of Network Camera Based on TMS320DM642 [Copy link]

There are many options for network camera solutions, but the mainstream products on the market generally choose two solutions: (1) CPU + ASIC. (2) Dual CPU structure, that is, an embedded CPU and a dedicated signal processing chip DSP. Due to the limitation of the processing power of the dedicated DSP chip, the video processing algorithms used in existing embedded network cameras are basically standards below H.263.

This article introduces a network camera design based on TMS320DM642 DSP. Its operating system, communication protocol, network protocol, audio and video processing software are all implemented on a TMS320DM642, which reduces the difficulty of development.

Figure 1 Network camera hardware schematic diagram

Figure 2 Video interface schematic diagram

Introduction to TMS320DM642 chip

TI's TMS320DM642 (hereinafter referred to as DM642) is a special DSP for multimedia applications. The DSP clock is up to 600MHz, with 8 parallel computing units and a processing capacity of 4800MIPS. It adopts a secondary cache structure and has a 64-bit external memory interface. It is compatible with IEEE-1149.1 (JTAG) boundary scan. In order to face multimedia applications, it also integrates 3 configurable video ports, McASP (Multi Channel Audio Serial Port) for audio applications, 10/100Mb/s Ethernet MAC and other peripherals. In view of the above advantages of DM642, this network camera system uses DM642 as the core to complete the real-time acquisition, compression and transmission of audio and video signals.

Hardware Design

The system circuit composition is shown in Figure 1. The video signal input from the camera and the audio signal input from the microphone are collected, converted into digital signals by A/D, and then sent to the DSP. The DSP compresses and encodes the audio and video signals at the source, and then transmits the data to the video monitoring center through the local area network or the Internet. The monitoring center can monitor multiple sites at the same time, receive or send alarm signals, and control the pan/tilt in real time through the asynchronous serial bus RS-485 as needed to adjust the direction and position of the camera.

Video capture circuit

The video decoding chip used in this system is Philips' SAA7115. The full TV signal input from the analog video input port is clamped, anti-aliased filtered, A/D converted, and YUV separated in the SAA7115. It is then converted into a BT.656 video data stream in the YUV to YCrCb conversion circuit and input into the compression core unit DM642. The three video ports VP0, VP1, and VP2 of DM642 are connected to the video codec chip.

In this system, there is only one video input, so the VP1 and VP2 ports are not used, and the VP0 channel is configured as an 8-bit BT.656 video input port. The line/field synchronization signals of the video data are included in the EAV (end of active video) and SAV (start of active video) time base signals of the BT.656 digital video data stream. The video port only needs the video sampling clock and sampling enable signal. The configuration of the internal register parameters of SAA7115 and the reading of the status are carried out through the I2C bus. The principle of the video interface is shown in Figure 2.

Audio input/output circuit

This system uses TI's high-performance stereo codec TLV320AIC23 (hereinafter referred to as AIC23) to collect and play audio signals. AIC23 is compatible with the I/O voltage of DM642 and can achieve seamless connection with the McASP interface of DM642.

In this system, AIC23 works in master mode, and the sampling word width of left and right channels is 16 bits. The data interface is in DSP mode. The working parameters and feedback status information of the internal registers are set through the I2C bus.

Due to the inherent characteristics of network transmission, it is impossible for audio data and video data to arrive at the monitoring center uniformly from the network camera end. If the network camera end does not perform any correction processing, it is difficult to ensure the synchronous output of audio and video. In order to achieve audio and video sampling synchronization, this paper uses the phase-locked loop PLL1708 to output a 27MHz clock from the LLC pin of SAA7115, and generates the master clock MCLK of AIC23 through PLL1708. Since the audio and video sampling signals use the same clock source, there will be no problem of audio and video being out of sync. The SCKO3 pin of PLL1708 outputs a default clock frequency of 18.433MHz, which is used as the input master clock MCLK of AIC23. The clock used inside AIC23 can be obtained by dividing the master clock MCLK by setting the register.

Ethernet interface circuit

This system uses LXT971 as the Fast Ethernet physical layer adaptive transceiver. Since LXT971 supports IEEE 802.3 standard, provides MII (media independent interface) interface, can support MAC, and DM642 has an Ethernet media access controller integrated inside, LXT971 can achieve seamless connection with DM642. The connection circuit is shown in Figure 3, where BH1102 is a 1:1 isolation transformer. After the data transmitted from DM642 is converted into data that can be received by the Ethernet physical layer by LXT971, it is transmitted to the Internet through the RJ-45 head.

Memory expansion circuit

DM642 has 16KB of L1 program cache, 16KB of L1 data cache and 256KB of L2 cache shared by program and data. But this is not enough to process image data directly, so two 32MB SDRAMs are added to store raw image data and 4MB of FLASH is used to store application programs. Both are mapped to the external data space of DM642.

CPLD Circuit

The CPLD used in this system is Xilinx's XC9572XL. The chip has 72 macrocells, 1600 logic gates, 5ns pin-to-pin logic delay, and 178MHz system frequency. The main functions of the CPLD are: address decoding for FLASH, UART, and CPLD asynchronous register space; generating 3-bit page select signals for FLASH; monitoring the level interrupt signal from the UART, converting it into an edge-triggered interrupt signal and sending it to the DSP.

RS-485 interface circuit

This interface is connected to the camera's pan/tilt to control the pan/tilt's rotation and adjust the direction and position of the camera. The RS-485 bus has strong anti-interference ability and can achieve multi-site long-distance communication. This compression card intends to use the UART chip SC16C550 and MAXIM's MAX487E to realize the transmission of RS-485 signals. The main function of SC16C550 is to convert the parallel signal transmitted by DSP into a serial signal. The receiver and transmitter inside SC16C550 each have a 16B FIFO, which can process serial signals at a rate of up to 3Mbps. MAX487E is an RS-485 bus interface chip that can work in full-duplex and half-duplex modes. The transmission rate can reach 2.5Mbps.

Power Circuit

The entire compression card is powered by a 5V DC transformer. This 5V transformer generates 1.4V and 3.3V voltages to power the DSP core and I/O ports respectively, and another 3.3V to power the video codec and other chips. Note that these two 3.3V power supplies should be designed separately to avoid power supply noise interference.

Since DSP requires two voltages, the coordination of the power supply system must be considered. During the power-on process, the core power supply should be powered on first, and at the latest, it should be powered on together with the I/O power supply. When turning off the power, turn off the core power supply first, and then turn off the I/O power supply. The reason for paying attention to the power supply sequence is that if only the CPU core is powered and the peripheral I/O is not powered, there will be no damage to the chip, but there will be no input/output capability. If on the contrary, the peripheral I/O is powered but the CPU core is not powered, then the transistors in the chip buffer/driver part will work in an unknown state, which is very dangerous.

To solve this problem, this article uses the switching power supply chip TPS54310PWP, and connects the 1.4V module's power output valid pin PG (power good) to the 3.3V module's enable voltage input pin EN. In this way, only when the 1.4V voltage is valid, the 3.3V voltage starts to power on, which ensures that the core voltage of DM642 is powered on before the I/O voltage.

Software Design

In this system, the H.264 standard is used for image compression. H.264 has a high coding efficiency. Under the same quality of reconstructed images, it can save about 50% of the bit rate compared with H.263. The code stream structure of H.264 has strong network adaptability, increased error recovery capability, and can adapt well to the application of IP and wireless networks. The audio codec adopts the G.729 algorithm. The network transmission adopts the RTP/RTCP protocol and multicast mode, which can ensure the quality of transmission. In terms of the operating system, the TI Reference Architecture 5 (RF5) based on DSP/BIOS is adopted. The application modules based on the RF5 operating system mainly include: audio and video acquisition module, compression encoding module, UART control module and network transmission module.

　　

This solution can realize almost all the functions of a network camera on a DM642 chip, and can perform real-time encoding and decoding of audio and video and real-time network transmission. It has high image quality, low development difficulty, and is easy to upgrade. It is an ideal network camera solution and can be widely used in video surveillance systems.