FPGA Design Tips: How to Use FPGA Clock Resources Correctly

Knowledge of DCM, PLL, PMCD, and MMCM is the foundation of a robust clock design strategy. Xilinx provides a wealth of clock resources in its FPGAs, and most designers use them more or less in their FPGA designs. However, for FPGA design novices, it is quite confusing when to use which of the four types of DCM, PLL, PMCD, and MMCM. None of Xilinx's current FPGAs contain all four resources at the same time (see Table 1).

　　Each of these four categories targets a specific application. For example, a digital clock manager (DCM) is suitable for implementing a delay-locked loop (DLL), a digital frequency synthesizer, a digital phase shifter, or a digital spectrum spreader. A DCM is also ideal for mirroring, routing, or rebuffering a clock signal. Another clock resource, a phase-matched clock divider (PMCD), can be used to implement a phase-matched distributed clock or a phase-matched delayed clock.

　　Phase-locked loops (PLLs) and mixed-mode clock managers (MMCMs) handle many of the same tasks, such as frequency synthesis, internal and external clock jitter filtering, clock deskew, etc. Both resources can also be used to mirror, forward, or rebuffer clock signals.

　　Keeping these common usages in mind can help clarify your clock selection process when you think deeply about the design implementation details. For long-term product development planning, compatibility between device families should be considered when developing an appropriate clock strategy. Let's take a closer look at these clock resources.

　　You can use a DCM to multiply input clock signals from clock sources to generate a higher-frequency clock signal. Similarly, you can divide input clock signals from high-frequency clock sources to generate a lower-frequency clock signal.

　　Digital Clock Manager

　　As the name implies, a digital clock manager (DCM) is a module that manages the clock architecture and helps shape and manipulate clock signals. The DCM contains a delay-locked loop (DLL) that can remove the skew of the DCM output clock signal based on the input clock signal, thereby avoiding clock distribution delays.

　　The DLL contains a delay element and a control logic link. The output of the delay element is the delay of the input clock. The delay time depends on the position of the delay element in the delay link. This delay is reflected as a phase change or phase shift for the original clock, which is called "digital phase shift". Figure 1 shows a typical DCM module in a Virtex-4 device. According to the Virtex-4FPGA User Guide (UG070, Version 2.6), there are three different DCM primitives in Virtex-4.

　　Generally speaking, a DLL is similar to a PLL. However, unlike a PLL, a DLL does not contain a voltage-controlled oscillator (VCO). A PLL stores both phase and frequency information at all times, while a DLL only stores phase information. Therefore, a DLL is slightly more stable than a PLL. Both types of DLLs and PLLs can be designed using analog and digital techniques, or a mix of the two. However, the DCM in Xilinx devices is a fully digital design.

　　Because DCMs can introduce delays in the clock path, you can use DCMs to accurately generate the timing of row and column access strobes for DRAMs, for example. Similarly, individual data bits on a data bus can arrive at different times. In order to correctly sample the data bits, the clock signal at the receiving end must be properly synchronized with the arrival of all data bits. If the receiver uses the transmit clock, it may be required to delay the clock signal from the transmitter to the receiver.

　　Sometimes a design may require a higher clock frequency to run the logic on the FPGA. However, only clock sources with low frequency outputs are available. In this case, a DCM can be used to multiply the input clock signals from the clock sources to generate a high frequency clock signal. Similarly, the input clock signals from the high frequency clock sources can be divided to generate a low frequency clock signal. This technique is called "digital frequency synthesis".

　　Designers use spread spectrum clocking to reduce the peak electromagnetic radiation of the clock signal by modulating the clock signal. The peak of an unmodulated clock signal produces high electromagnetic radiation. However, after modulation, the electromagnetic radiation is spread over a range of clock frequencies, thereby reducing the radiation at all frequencies. Generally speaking, spread spectrum clocking is required when certain maximum electromagnetic radiation requirements need to be met and when high-speed processing is performed on the FPGA, such as the deserializer used in the receiver of a communication system. Therefore, the DCM in the FPGA will multiply the input spread spectrum clock signal to generate a high-frequency clock signal internally. The output of the DCM must accurately follow the spread spectrum clock to maintain phase and frequency alignment and update the de-skew and phase shift. Deterioration of the DCM phase and frequency alignment will reduce the skew margin of the receiver.

　　Mirroring the clock requires sending the clock signal out of the FPGA device and then receiving it back. This method can be used to deskew board-level clock signals for multiple devices. DCM can send the clock signal from the FPGA to another device. This is because the input clock signal of the FPGA cannot be directly routed to the output pin. There is no such routing path available. If you only need to send the clock signal, then using a DCM to send the clock signal to the output pin can ensure the fidelity of the signal. Another option is to connect the DCM output to the ODDR flip-flop before the clock signal is sent. Of course, you can choose not to use a DCM and only use ODDR to send the clock signal. Often the clock driver needs to drive the clock signal to multiple components of the design. This increases the load on the clock driver, causing clock skew and other problems. In this case, clock buffers are needed to balance the load.

　　The clock can be connected to a series of logic blocks on the FPGA. To ensure that the clock signal has appropriate rise and fall times at registers far away from the clock source (thus keeping the input and output delays within the allowed range), a clock buffer needs to be inserted between the clock driver and the load. DCM can be used as a clock buffer between the clock input pin and the logic block.

　　Finally, you can also use a DCM to convert an input clock signal to a differential I/O standard signal. For example, a DCM can convert an input LVTTL clock signal to an LVDS clock signal for transmission.

　　Phase-matched clock dividers

　　Designers can use a phase-matched clock divider (PMCD) to generate phase-matched, divided input clock signals. This is similar to the DCM frequency synthesis of divided clocks. PMCDs can also generate clock signals that are phase-matched but delayed in the design. In the latter case, the PCMD is able to maintain edge alignment, phase relationship, and skew between the input clock signal and other PMCD input clock signals. Unlike DCMs, the clock signals generated by the existing PMCDs in Xilinx devices only divide by 2, 4, and 8, while the divider value is configurable. This means that the frequency of the clock signal generated by the PMCD is 1/2, 1/4, and 1/8 of the input clock signal. In Xilinx devices such as Virtex-4 FPGAs, the PMCD is located next to the DCM and in the same column as it. There are two PMCD-DCM pairs in each column. Therefore, the output of the DCM can drive the input of the PMCD.

　　Since the DCM also handles deskew, designers can use PMCD without DCM as long as deskew clocks are not required. Two PMCDs in a column can also be connected together through dedicated pins. Figure 2 shows the PMCD primitive in Virtex-4 devices. For more information, refer to the Virtex-4FPGA User Guide (UG070, Version 2.6).

　　Mixed-Mode Clock Manager

　　Another type of clock resource, the mixed-mode clock manager (MMCM), is used to generate different clock signals with a set phase and frequency relationship to a given input clock. However, unlike DCM, MMCM uses PLL to do this. The clock management module (CMT) in Virtex-6 FPGA has two MMCMs, while the CMT in Virtex-7 has one MMCM and a PLL. The MMCM in the Virtex-6 device does not have a spread spectrum function, so the spread spectrum on the input clock signal will not be filtered and will be directly transmitted to the MMCM output clock. But the MMCM of Virtex-7 FPGA does have a spread spectrum function.

　　The MMCMs in the Virtex-6 FPGA require the insertion of a calibration circuit to ensure the correct operation of the MMCM after a user reset or user power down. Xilinx ISE Design Suite version 11.5 and later can automatically insert the necessary calibration circuit during the MAP phase of the design. If using earlier versions of Xilinx ISE, it is necessary to manually insert the calibration circuit using the design files provided by Xilinx Technical Support. Finally, it is important to note that when porting this design for implementation in ISE version 11.5 or later, the calibration circuit must be manually removed or the automatic insertion feature must be disabled by appropriately setting the synthesis properties on each MMCM. For more information, see Xilinx Answer Record AR#33849.

　　This is not an issue for MMCMs in 7 series devices, as these FPGAs are only supported by ISE 13.1 and later and the new Vivado design suite. The dedicated routing between MMCMs provided in the Virtex-6 family allows users to use global clock resources for the rest of the design.

　　Figure 3 shows the MMCM primitive in the Virtex-6 FPGA. For detailed descriptions of each port, refer to the Virtex-6 FPGA Clock Resources User Guide (UG362, Version 2.1). Figure 4 shows the MMCM primitive in the Xilinx 7 series FPGA. For detailed descriptions, refer to the 7 series FPGA Clock Resources User Guide (UG472, Version 1.5).

　　Phase-Locked Loop

　　Designers use phase-locked loops (PLLs) primarily for frequency synthesis. A PLL can be used to generate multiple clock signals from a single input clock signal. In combination with a DCM, it can also be used as a jitter filter. PLLs are available in Spartan-6, Virtex-5, and 7 series FPGAs. Spartan-6 and Virtex-5 both have dedicated "DCM to PLL" and "PLL to DCM" routing. The PLL outputs in Spartan-6 and Virtex-5 are non-spread spectrum. For both devices, a PLL can be used instead of a DCM if the design uses multiple different clocks. The PLL clock output has a wide range of configurations, while the DCM output is predetermined and not configurable. The choice of PLL and DCM again depends on the design requirements. However, if phase shifting is required, a DCM should be explicitly selected.

　　At the same time, the PLL in the 7 series devices does not implement as many functions as the MMCM. So although the MMCM is built on the PLL architecture, there are also independent PLLs in the 7 series devices. Figure 5 shows the PLL primitives in the Virtex-5 FPGA. For a detailed description of each port, please refer to the Virtex-5 User Guide (UG190, version 5.4).

　　Design Migration

　　It is important to understand the differences between the four major clock resources and their availability in different device families. Also, similar resources (such as DCMs) may not be identical in functionality across different families. For example, the DCMs in Spartan-6 FPGAs support spread-spectrum clocking, but the DCMs in Virtex-5 and Virtex-5 devices do not.

　　When planning for future migration of designs to higher-end families, in addition to ensuring functionality, it is also important to select the correct clock resource for a given design. As shown in Table 1, the MMCMs in the Virtex-6 and 7 families are backward compatible with the DCMs in previous families. However, it is necessary to judge the extent to which backward compatibility is supported, because all of these clock resources are multifunctional and provide a variety of different functions related to clocking. When making long-term product development plans, it is necessary to have a good understanding of compatibility.