Simplifying the FPGA Implementation of UART Functions

1 Introduction

In the ARM+FPGA system structure, the simplest way to achieve communication between the ARM-based embedded processor and the FPGA is through the asynchronous serial interface EIARS232C. Consider choosing an embedded processor (for example, EP7312) with an integrated UART (Universal Asynchronous Receiver / Transmitter) controller, so that the embedded processor side has the ability to send and receive communications using the asynchronous serial interface. However, the FPGA does not have a CPU control unit inside and cannot handle interrupts generated by the UART controller. Therefore, the FPGA side cannot use the existing UART controller to form an asynchronous serial interface, and the function of the UART controller must be integrated into the FPGA.

The ARM and FPGA in the same system are connected over short distances. The asynchronous serial communication between them does not require complete UART functions. The communication control signal lines in the RS232 standard can be omitted, and only the receiving and sending data lines and the ground line are retained. This greatly omits the FPGA programming implementation of the UART function. The embedded processor EP7312 has two 16550 type UARTs that support asynchronous serial communication RS232. UART1 not only has TX, RX, but also supports Modem control signals. UART2 only has standard TX, RX and ground signals, which can just use UART2 to communicate with FPGA. Figure 1 is a simplified schematic diagram of asynchronous serial communication connection.

2 Simplifying the FPGA Implementation of UART Functions

This article will discuss in detail the implementation of simplified UART functions in FPGAs. Let's briefly review the data format of asynchronous serial communication. Figure 2 shows the bit timing relationship of a data byte sent serially in asynchronous transmission (the parity bit is not included in the figure). A complete byte of information is sent first as a logic "0" bit as the start bit, followed by 8 data bits, and then 1, 1+1/2 or 2 stop bits. The logic "1" bit, the data line is idle when it is high or "1". In the 8-bit data portion of the character, the least significant bit of the data is sent first, and the most significant bit is sent last. The duration of each bit is fixed and is controlled by the transmitter's local clock. The number of data bits sent per second is the "baud rate". The start bit and stop bit play an important role. Obviously, they mark the beginning and end of each character, but more importantly, they enable the receiver to resynchronize its local clock with each new character received. Asynchronous communication has no reference clock signal. The transmitter may send data at any time, and the occurrence time of any edge can correctly sample the next 10 to 11 bits (including start bit, data bit and stop bit). The receiver's clock is not the same as the transmitter's clock. Therefore, the interval between the receiver's sampling points is different from the bit interval time determined by the transmitter's clock. The receiver must not let its relative clock speed cause sampling errors.

In comparison, the UART transmitter part is relatively easy to implement the process of sending serial data, as long as the duration of the data level to be sent is timed. The following is a detailed description of the FPGA implementation method of the UART receiver part.

2.1 FPGA Implementation of UART Receiver

According to the above description, since the serial data frame is asynchronous with the receiving clock, the key to the realization of the receiver function is the synchronization of the receiver clock with each received character. An effective method is that the receiver uses a high-rate clock to sample the serial data, and the sampling frequency is usually an integer multiple of the bit clock frequency. Theoretically, the higher the multiple, the higher the resolution of each bit of the received data. In practice, the maximum selection is generally 16 times.

The receiver should sample each bit as close to the center of the bit period as possible. If the receiver can predict the start of the start bit well, it can wait half a bit period after the falling edge of the start bit before sampling the data bit. After that, the receiver samples one data bit every bit period until the last bit is received. If the frequency of the receiving clock is close enough to the transmitting clock so that the last bit can be sampled within half a period from the exact center of the bit, the above scheme will work correctly. This means that the increase and decrease of the receiving clock relative to the transmitting clock within 10 to 11 clock cycles should be less than half a bit time interval. Therefore, the error tolerance of the two clocks on both the transmitter and the receiver is required to be within 5%.

The receiver in this article adopts the 5x sampling method, that is, the receiving sampling frequency is 5 times the serial data bit frequency. Figure 3 is a magnified start bit and part of the data bits in Figure 2, and each information bit is divided into 5 equal parts, and the time width of each equal part is set to Ts. When the information bit is sampled at 5 times the frequency, each information bit may be sampled 5 times. When in the idle state and detecting the start bit, the earliest time when the start bit is detected at a low level must fall in the S0 shadow area, and the specific sampling point will change randomly in the S0 shadow area each time. After the start bit is detected at a low level, the interval of 7×Ts is exactly the middle 1/5 of the first data bit (D2 shadow area in Figure 3). The sampling intervals of the data bits and stop bits thereafter are all 5×Ts, and all sampling points fall in the middle 1/5 of the code element, so the sampled data is the most reliable. The generation of the sampling clock is controlled by a counter, and the counter clock is 5 times the bit clock.

In order to avoid start bit detection errors caused by noise, the start bit is sampled twice. From the idle state, after the first sampling is low level, it is sampled again after an interval of 2 Ts. If it is still low level, it is recognized as a valid start bit; if it is high level, it returns to the idle state and waits for resynchronization.

In addition, a protection mechanism can also be added when sampling the stop bit: When the stop bit sampling value is high, the synchronization and data are considered correct and loaded into the data register; otherwise, the synchronization or transmission is considered wrong, and the character sampled this time is invalid and discarded. The simplified UART functional block diagram is shown in Figure 4. In the UART controller 16550 of EP7312, the depth of FIFO is 16 B. In actual FPGA implementation, RAM can be used to replace FIFO according to different specific applications. This article only describes the implementation method of the receiver and transmitter in Figure 4.

When the hardware description language VHDL is used for programming, the key part of the receiver 5 times speed sampling method uses a state machine, and the state transition diagram is shown in FIG5 .

2.2 FPGA Implementation of UART Transmitter

The FPGA implementation of the UART transmitter is much simpler than that of the receiver. When there is no data to be sent, the transmit data register is empty and the transmitter is in an idle state; when the transmit data register is full, the transmitter sends the start bit, and the 8 data bits are loaded into the transmit shift register in parallel. The stop bit follows the data bit to indicate the end of the data frame. Only when the transmit data register is empty can the data to be sent in the RAM or FIFO be loaded. A counter is used in the program to ensure that the timing of each bit cycle is correct. A state machine is still used to describe the transmission process. Figure 6 is a schematic diagram of the state transition of the transmitter state machine.

3 Simulation and Conclusion

Here we use the ACTEL APA600 series FPGA chip and the MENTOR ModelSim simulation tool. Figure 7 is a functional simulation timing diagram of the receiver module, in which only the time length of a received data frame is intercepted. It can be seen from Figure 7 that a false start bit is correctly judged, the receiver is synchronized with the received data, and the serial data is accurately received. State machine status: i represents idle; rx represents start bit confirmation; s represents data sampling and stop state confirmation; g represents data correct reception.

Figure 8 is a timing diagram of transmitter module function simulation, which also captures only one frame length of transmitted data. In Figure 8, the state machine states: first represents idle; second (the time is too short, the corresponding text is not shown in the figure) and third represent transmitted data and stop bits.

We have applied the above-mentioned programming method for implementing simplified UART functions to the compilation/disassembly and sending/receiving serial information frame modules of the ARM+FPGA structure system. It works stably and has high practical value.