The difference between cpld and fpga

Systematic comparison, shared with you:
Although FPGA and CPLD are both programmable ASIC devices with many common features, they have their own characteristics due to the differences in the structures of CPLD and FPGA:
① CPLD is more suitable for completing various algorithms and combinational logic, while FPGA is more suitable for completing sequential logic. In other words, FPGA is more suitable for structures with rich triggers, while CPLD is more suitable for structures with limited triggers and rich product terms.
② The continuous wiring structure of CPLD determines that its timing delay is uniform and predictable, while the segmented wiring structure of FPGA determines the unpredictability of its delay.

③ In terms of programming, FPGA has greater flexibility than CPLD. CPLD is programmed by modifying the logic function with fixed internal circuits, while FPGA is mainly programmed by changing the wiring of internal connections; FPGA can be programmed under logic gates, while CPLD is programmed under logic blocks.

④ FPGA has a higher integration level than CPLD, and has a more complex wiring structure and logic implementation.

⑤ CPLD is more convenient to use than FPGA. CPLD programming adopts E2PROM or FASTFLASH technology, does not require external memory chip, and is simple to use. However, the programming information of FPGA needs to be stored in external memory, and the method of use is complicated.

⑥ CPLD is faster than FPGA and has greater time predictability. This is because FPGA is gate-level programming, and the CLBs are interconnected in a distributed manner, while CPLD is logic block-level programming, and the interconnection between its logic blocks is lumped.

⑦ In terms of programming method, CPLD is mainly based on E2PROM or FLASH memory programming, and the number of programming times can reach 10,000 times. The advantage is that the programming information will not be lost when the system is powered off. CPLD can be divided into two categories: programming on the programmer and programming in the system. Most FPGAs are based on SRAM programming. The programming information is lost when the system is powered off. Each time the power is turned on, the programming data needs to be rewritten into the SRAM from the outside of the device. Its advantages are that it can be programmed any number of times and can be programmed quickly during work, thus achieving dynamic configuration at the board level and system level.

⑧CPLD has good confidentiality, while FPGA has poor confidentiality.

⑨Generally speaking, the power consumption of CPLD is greater than that of FPGA, and the higher the integration, the more obvious it is.
With the increase in the density of complex programmable logic devices (CPLDs), digital device designers are both flexible and easy when carrying out large designs, and their products can enter the market quickly. Many designers have already experienced the advantages of CPLDs such as ease of use, predictable timing, and high speed. However, in the past, due to the limitations of CPLD density, they had to turn to FPGAs and ASICs. Now, designers can experience the benefits of CPLDs with densities as high as hundreds of thousands of gates.
The CPLD structure uses 1 to 16 product terms in a logic path, so the running speed of large and complex designs can be predicted. Therefore, the operation of the original design is predictable and reliable, and it is easy to modify the design. CPLD is flexible in nature, has simple timing, and excellent routing performance, and users can change their designs while keeping the pinout unchanged. Compared with FPGA, CPLD has more I/O and smaller size.
Today, communication systems use many standards, and devices must be configured to support different standards according to customer needs. CPLD allows devices to make corresponding adjustments to support multiple protocols and change functions as standards and protocols evolve. This brings great convenience to system designers because they can start hardware design before the standard is fully mature, and then modify the code to meet the requirements of the final standard. CPLD has better speed and latency characteristics than pure software solutions, its NRE cost is lower than ASIC, it is more flexible, and products can be put into the market faster. The advantages of CPLD programmable solutions are as follows:
● Rich logic and memory resources (Cypress Delta39K200 has more than 480 Kb of RAM)
● Flexible timing model with redundant routing resources
● Very flexible to change pinout
● Can be reprogrammed after installation on the system
● Large number of I/Os
● Integrated memory control logic with guaranteed performance
● Provides single-chip CPLD and programmable PHY solutions
Due to these advantages, the design modeling cost is low, the design can be added or the pinout can be changed at any stage of the design process, and it can be quickly put on the market. The
structure of CPLD
CPLD is a coarse-grained programmable logic device. It has rich logic resources (i.e., a high ratio of logic gates to registers) and highly flexible routing resources. The routing of CPLD is connected together, while the routing of FPGA is separated. FPGA may be more flexible, but includes many jumpers, so the speed is slower than CPLD.
CPLD is arranged in the form of an array of clusters, connected by horizontal and vertical routing channels. These routing channels send signals to or from the pins of the device and connect the logic groups inside the CPLD.


CPLDs are called coarse-grained because the logic groups are large compared to the number of routes. CPLD logic groups are much larger than the basic unit of FPGAs, so FPGAs are fine-grained.
Functional Blocks of CPLDs
The most basic unit of CPLDs is the macrocell. A macrocell contains a register (using up to 16 product terms as its inputs) and other useful features.
Because each macrocell uses 16 product terms, designers can implement a large amount of combinational logic without adding additional paths. This is why CPLDs are considered "logic-rich". Macrocells

are arranged in logic blocks (LBs), and each logic block consists of 16 macrocells. Macrocells perform an AND operation and then an OR operation to implement combinational logic.

Each logic group has 8 logic blocks, and all logic groups are connected to the same programmable interconnect matrix. Each group
also contains two single-port logic group memory blocks and one multi-port channel memory block. The former has 8,192b of memory per block, and the latter contains 4,096b of dedicated communication memory and can be configured as single-port, multi-port, or FIFO with dedicated control logic.
What are the benefits of CPLDs? One of the benefits of a CPLD
with a large number of I/Os
is that it can provide more I/Os for a given device density, sometimes up to 70%.
Simple Timing Model
CPLDs are superior to other programmable structures in that they have a simple and predictable timing model. This simple timing model is mainly due to the coarse-grained nature of the CPLD.
CPLDs can provide a wide range of equal states in a given time, regardless of routing. This ability is key to design success and can speed up not only the initial design work, but also the design debugging process.
Advantages of Coarse-Grained CPLD Structure
CPLDs are coarse-grained structures, which means that the path in and out of the device passes through fewer switches and correspondingly less delay. Therefore, compared with equivalent FPGAs, CPLDs can operate at higher frequencies and have better performance.
Another benefit of CPLDs is that they compile software quickly because their easy-to-route structure makes the task of laying out the design easier to perform.

Advantages of Fine-Grain FPGA Structure
FPGAs are fine-grained, which means there are fine-grain delays between each unit. FPGAs are quite fast if small amounts of logic are packed closely together. However, as the design density increases, signals have to pass through many switches, and routing delays increase rapidly, which weakens the overall performance. The coarse-grained structure of CPLDs can adapt well to changes in design layout.


Flexible Output Pins
The coarse-grained structure and timing characteristics of CPLDs are predictable, so designers can still change output pins later in the design process while the timing remains unchanged.
New CPLD Packages
CPLDs are available in a variety of densities and package types, including single-chip self-boot solutions. Self-boot solutions integrate FLASH memory and CPLDs in a single package, eliminating the need for external boot units, thereby reducing design complexity and saving board space. Within a given package size, there is a higher density of devices sharing pin outputs. This provides designers with the convenience of "enlarging" the design without changing the pin output on the board.

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It is common to see people use various encoding methods in state machine design. So, in general, what is the basis for choosing this encoding method?
We know that there are three most commonly used encoding methods in digital logic design: binary, Gray code, and One-hot encoding. One-hot encoding uses a set of code elements, each of which has only 1 bit valid, such as
IDLE = 0001,
WRITE = 0010,
READ = 0100,
WAIT = 1000.
The decoding part of this encoding can be the simplest, so the characteristics of One-hot encoding can be summarized:
the least combinational logic, the most triggers, and the highest working clock frequency.
A minimum structural unit (CLB/LE) of FPGA contains a lookup table (to implement combinational logic) and DFF (to implement sequential logic). The best result of layout and routing is to use both the lookup table and DFF in the same structural unit, but in most cases only one of the resources is used, so the other resources are idle and wasted. However, there are very few DFF resources in CPLD. Therefore, one-hot coding is more suitable for FPGA design, but not for CPLD design. Binary coding should be selected in CPLD. In
IC design, comprehensive consideration should be given. Because one-hot coding using DFF will greatly increase the design area (die size), binary coding should be used as much as possible under the condition that the timing can be met. Gray code is the best choice in terms of the trade-off between area and speed. Of course, Gray code has many other good features, which are not within the scope of this discussion. General synthesis tools allow users to choose from these three codes when synthesizing state machines. The basic basis is as mentioned above.

Conversion between binary and Gray code
The rule for converting natural binary code to binary Gray code is to retain the highest bit of the natural binary code as the highest bit of the Gray code, and the second highest bit of the Gray code is the high bit of the binary code and the second highest bit are XOR, and the rest of the Gray code is similar to the second highest bit
The rule for converting binary Gray code to natural binary code is to retain the highest bit of the Gray code as the highest bit of the natural binary code, and the second highest bit of the natural binary code is the high bit of the natural binary code and the second highest bit of the Gray code are XOR, and the rest of the natural binary code is similar to the second highest bit of the natural binary code

The design requirements of the state machine in FPGA or CPLD under high-speed environment can be met by reducing the logic delay between registers to increase the operating frequency, or by optimizing the data path during data processing through pipeline design. This article provides the specifications, analysis methods and optimization methods for the design of state machines in high-speed environments using these technologies, and gives corresponding examples.

In order to make the state machine design in FPGA or CPLD meet the requirements of high-speed environments, design engineers need to realize the following points: register resources and logic resources are no longer the problem, and the FPGA or CPLD logic resources or register resources occupied by the state machine itself are very small; the state machine operates serially on the overall data flow. If you want the delay of data processing to be very small, you must increase the parallelism of the operation and compress the path length of the state transfer in the state machine; the state and transfer conditions of the state machine should be reasonably allocated under high-speed environments. This article will illustrate this with practical application cases.

State Machine Design Specifications

1. Use one-hot encoding for state encoding
There are three main types of state encoding in a state machine: sequential encoding, one-hot encoding, and encoding that does not belong to these two types. For example, for a state machine with 5 states (State0 to State4), the state encodings in the sequential encoding method are: State0-000, State1-001, State2-010, State3-011, State4-100. The one-hot encoding method is as follows: State0-00001, State1-00010, State2-00100, State3-01000, State4-10000. For self-defined encoding, it is very different. For example, trying to use the state bit of the state machine directly as the required output signal may increase the difficulty of design.

Using one-hot encoding makes the logic implementation simpler, because a state only needs to be indicated by one bit, and the number of state registers added for this purpose can be ignored relative to the entire design. One bit is valid for at least two meanings: for each state bit, the bit is 1 corresponding to a unique state. To determine whether the current state is this state, it is only necessary to determine whether the state bit is 1; if the bit at the input of the state register is 1, the next state will be transferred to this state. To determine whether the next state is this state, it is only necessary to determine whether the bit in the signal representing the next state is 1.

2. Reasonable allocation of state transfer conditions
In the state transfer diagram, each state has corresponding output and input lines. The number of input lines from different states to this state through different transfer conditions cannot be too many. For analysis, using the CPLD design using AND or logic, if there are too many such input lines, more product terms and OR logic will be required, which requires more levels of logic cascade to complete, thereby increasing the delay between registers; for FPGA, multiple levels of lookup tables are required to implement the corresponding logic, which will also increase the delay. The application model of the state machine is shown in Figure 1.

Analysis methods for state machine design
The analysis methods for state machine design can be divided into two types: one is process processing analysis, that is, analyzing how data is processed step by step, and defining the corresponding processing steps as different states in sequence. This method can analyze very complex state machines, similar to the analysis of writing a software program, and typical designs include read and write operations and data packet byte analysis; the other method is key condition analysis, that is, determining the corresponding state based on the logical conditions of reference signals, such as empty or full indications, start or end, handshake response signals, etc. There is no strict boundary between these two analysis methods. In actual state machine design analysis, these two methods are often used in combination. The following describes these two analysis methods respectively.

1. Process processing analysis
For example, in a design of reading a data packet in a ZBT SRAM, it is necessary to determine whether the read operation of a packet is completed based on whether the EOP (End of Packet) signal in the read data is 1. Due to the delay in reading the data, more data will be read from the ZBT SRAM. For this reason, a signal VAL_out can be designed to filter out the extra data.

According to the order of data arrival and the number of clock cycles occupied, a state machine as shown in Figure 2 can be designed (this article assumes: the current state in the text description and illustration is represented by s_State[n:0], which is the output of the state register; the next state next_State[n:0] is the input of the state register; the logical relationship between the signals is represented by symbols in the Verilog language (or C language); #R indicates that it needs to pass through a first-level register, and the output signal corresponds to the output end of the register). The state machine first determines whether the packet has reached the end of the packet. If so, it enters 6 waiting states in sequence. The data in the waiting state is invalid. After the 6 waiting states are completed, the data will be processed normally.

2. Key condition analysis
Figure 3 is a block diagram of a high-speed data packet distribution processing of a router line card. The higher-rate data packets are sent to two lower-rate data paths (i.e., written to FIFO1 or FIFO2) in units of packets through the distribution module.

For the design of the distribution module, the key reference signals are EOP and the almost full signals AF1 and AF2. Referring to EOP, one packet can be processed each time, and referring to AF1 and AF2 signals can determine which FIFO the corresponding packet should be written to. The distribution algorithm is: if FIFO1 is not full (AF1=0), the data packet will be written into FIFO1; if FIFO1 is about to be full and FIFO2 is not full (AF1=1, and AF2=0), the next data packet will be written into FIFO2; if both FIFO1 and FIFO2 are full (AF1=1 and AF2=1), the packet drop state is entered. The state machine description is shown in Figure 4: in the UseFifo1 state, the data packet will be written into FIFO1, and in the UseFifo2 state, the data packet will be written into FIFO2. In the packet drop state, the data packet will be discarded, and the packet drop count enable DropCountEnable is provided.

Further optimization of the state machine
1. Using the one-bit effective encoding method HSPACE=12 ALT="Figure 2: State machine for filtering the packet data read from the ZBT RAM."">
As mentioned above, the operating frequency of the state machine is related to the number of incoming lines corresponding to the different transition conditions of each state in the state machine. If the transition conditions to a state are the same but the number of incoming lines is very large, its logical implementation is likely to be not complicated. In the single-bit encoding mode, for a certain state, if all other states go to this state through the same transition condition, then its logic implementation can be simplified.
Example 4: In the single-bit encoding mode, in the state bit s_State[n:0],
s_State[1] | s_State[2] | ... | s_State[n]=1 is equivalent to s_State[0]=1, then
next_State[0]=(s_State[0]&S) | (s_State[1]&T) | (s_State[2]&T) | ... | (s_State[n]) can be simplified to:
next_State[0]=(s_State[0]&S) | ((~s_State[0])&T), and the number of input signals on the right side is greatly reduced.

2. Use the enable signal of the register
Most FPGA or CPLD registers provide an enable terminal. If all state machine transitions must meet at least a certain condition, then this condition can be achieved through the enable signal connection, thereby reducing the logic complexity of the register input terminal. As in the above example, the transition between different states must be based on the premise that EOP is 1, so this signal can be designed as an enable signal.

3. Write code in combination with the internal logic unit structure of the selected FPGA or CPLD
Taking Xilinx FPGA as an example, two 4-input lookup tables and related configuration logic in one unit can realize the most complex logic with 5 signal inputs, or simple logic with 8 to 9 signals (such as full AND or full OR), and the delay is a one-level lookup table and configuration logic delay; if the outputs of the four 4-input lookup tables of adjacent units are connected to a 4-input lookup table, then the most complex 6-input logic can be realized, and two-level lookup table delays and related configuration logic delays are required. More complex logic requires more cascades to achieve. For high-speed state machines, the logic source of the state register input can be controlled within 7 signals as much as possible, so as to autonomously control the number of cascades of the lookup table and increase the operating frequency of the design.

4. By modifying the state machine
If a state machine cannot meet the operating frequency requirements, the design must be modified according to the maximum delay path. The usual methods are: changing the state settings, adding new states or deleting certain states, simplifying the transfer conditions and the number of transfers connected to a single state; modifying the transfer condition settings, including changing the combination of transfer conditions, and changing the complex logic to a logic that is hierarchically output by registers and then formed by register signals. The latter will change the signal timing, so the state settings may need to be changed.

5. Use parallel logic
In many cases, there may be a lot of key signals to refer to. If you directly design the state machine with reference to these key signals, the results may be very complex, and the output or input lines of individual states will be very many, which will reduce the operating frequency. You can consider designing parallel logic to provide the key signals of the state machine and the required intermediate results. The state machine is responsible for maintaining the parallel logic and generating the data processing process. Parallel logic should be designed hierarchically, with registers between levels, so as to reduce the delay from register to register.

Figure 5 shows a state machine using parallel logic. This design is used to send data in FIFO1 to 4 to four data paths using a single data bus. The parallel logic in this design generates the path and FIFO selection results for each operation. The state machine is responsible for controlling the flow of each operation: in the "Idle" state, if there are data packets to read in FIFO1 to 4, it enters the "Schedule" state; after obtaining the scheduling result, "Schedule" passes through a "Wait" state, and then enters the "ReadData" state to read the data, and starts counting at the same time. When the count reaches the specified value or the end of the data packet is read, it enters the idle state "Idle", and the cycle continues.

Pipeline Design
Pipelining design is to divide the logic operation executed in one clock cycle into several smaller operations and complete them at a higher clock speed. The logic in Figure 6a is divided into three small parts in Figure 6b. If its Tpd is T, the maximum clock frequency of the circuit is 1/T. In Figure 6b, assuming that the Tpd of each part is T/3, its clock frequency can be increased to 3 times the original, so the data flow per unit time can reach 3 times the original. The cost is that the output signal lags behind the input by 3 cycles, the timing is changed (the total delay of the output signal in Figure 6b is the same as that in Figure 6a, but the data throughput is improved), and the register resources are increased. FPGA has abundant register resources.

This article emphasizes increasing the operating frequency of the state machine by reducing the logic delay between registers. The starting point is the same as that of pipeline design. The difference is that the pipeline emphasizes the optimization of the data path during data processing, while this article emphasizes the optimization of the control logic in the state machine.

Meally＆Moore state machine typical program

Verilog

// Example of a 5-state Mealy FSM

module mealy (data_in, data_out, reset, clock);

output data_out;

input [1:0] data_in;

input reset, clock;

reg data_out;

reg [2:0] pres_state, next_state;

parameter st0=3'd0, st1=3'd1, st2=3'd2, st3=3'd3, st4=3'd4;

// FSM register

always @ (posedge clock or negedge reset)

begin: statereg

if(!reset)// asynchronous reset

pres_state = st0;

else

pres_state = next_state;

end // statereg

// FSM combinational block

always @(pres_state or data_in)

begin: fsm

case (pres_state)

st0: case(data_in)

2'b00: next_state=st0;

2'b01: next_state=st4;

2'b10: next_state=st1;

2'b11: next_state=st2;

endcase

st1: case(data_in)

2'b00: next_state=st0;

2'b10: next_state=st2;

default: next_state=st1;

endcase

st2: case(data_in)

2'b0x: next_state=st1;

2'b1x: next_state=st3;

endcase

st3: case(data_in)

2'bx1: next_state=st4;

default: next_state=st3;

endcase

st4: case(data_in)

2'b11: next_state=st4;

default: next_state=st0;

endcase

default: next_state=st0;

endcase

end // fsm

// Mealy output definition using pres_state w/ data_in

always @(data_in or pres_state)

begin: outputs

case(pres_state)

st0: case(data_in)

2'b00: data_out=1'b0;

default: data_out=1'b1;

endcase

st1: data_out=1'b0;

st2: case(data_in)

2'b0x: data_out=1'b0;

default: data_out=1'b1;

endcase

st3: data_out=1'b1;

st4: case(data_in)

2'b1x: data_out=1'b1;

default: data_out=1'b0;

endcase

default: data_out=1'b0;

endcase

end // outputs

endmodule

Verilog

// Example of a 5-state Moore FSM

module moore (data_in, data_out, reset, clock);

output data_out;

input [1:0] data_in;

input reset, clock;

reg data_out;

reg [2:0] pres_state, next_state;

parameter st0=3'd0, st1=3'd1, st2=3'd2, st3=3'd3, st4=3'd4;

//FSM register

always @(posedge clock or negedge reset)

begin: statereg

if(!reset)

pres_state = st0;

else

pres_state = next_state;

end // statereg

// FSM combinational block

always @(pres_state or data_in)

begin: fsm

case (pres_state)

st0: case(data_in)

2'b00: next_state=st0;

2'b01: next_state=st4;

2'b10: next_state=st1;

2'b11: next_state=st2;

endcase

st1: case(data_in)

2'b00: next_state=st0;

2'b10: next_state=st2;

default: next_state=st1;

endcase

st2: case(data_in)

2'b0x: next_state=st1;

2'b1x: next_state=st3;

endcase

st3: case(data_in)

2'bx1: next_state=st4;

default: next_state=st3;

endcase

st4: case(data_in)

2'b11: next_state=st4;

default: next_state=st0;

endcase

default: next_state=st0;

endcase

end // fsm

// Moore output definition using pres_state only

always @(pres_state)

begin: outputs

case(pres_state)

st0: data_out=1'b1;

st1: data_out=1'b0;

st2: data_out=1'b1;

st3: data_out=1'b0;

st4: data_out=1'b1;

default: data_out=1'b0;

endcase

end // outputs

endmodule // Moore

Using state machines as clock generation circuits - unique but most accurate (common method in CPU design)

Introducing a clock generator - unique but most accurate (common method in CPU design)
The clock generator clkgen uses the external clock signal clk to generate a series of clock signals clk1, fetch, alu_clk to other parts of the CPU. Among them, fetch is the eight-frequency signal of the external clock clk. The rising edge of fetch is used to trigger the CPU controller to start executing an instruction. At the same time, the fetch signal will also control the address multiplexer to output the instruction address and data address. The clk1 signal is used as the clock signal of the instruction register, accumulator, and state controller. Alu_clk is used to trigger the arithmetic logic unit.
module clk_gen (clk,reset,clk1,clk2,clk4,fetch,alu_clk);
input clk,reset;
output clk1,clk2,clk4,fetch,alu_clk;
wire clk,reset;
reg clk2,clk4,fetch,alu_clk;
reg[7:0] state;
parameter S1 = 8'b00000001,
S2 = 8'b00000010,
S3 = 8'b00000100,
S4 = 8'b00001000,
S5 = 8'b00010000,
S6 = 8'b00100000,
S7 = 8'b01000000,
S8 = 8'b10000000,
idle = 8'b00000000;

assign clk1 = ~clk;

always @(negedge clk)
if(reset)
begin
clk2 <= 0;
clk4 <= 1;
fetch <= 0;
alu_clk <= 0;
state <= idle;
end
else
begin
case(state)
S1:
begin
clk2 <= ~clk2;
alu_clk <= ~alu_clk;
state <= S2;
end
S2:
begin
clk2 <
= ~clk2; clk4 <= ~clk4;
alu_clk <= ~alu_clk;
state <= S3;
end
S3:
begin
clk2 <= ~clk2;
state <= S4;
end
S4:
begin
clk2 <= ~clk2;
clk4 <= ~clk4;
fetch <= ~fetch;
state <= S5;
end
S5:
begin
clk2 <= ~clk2;
state <= S6;
end
S6:
begin
clk2 <= ~clk2;
clk4 <= ~clk4;
state <= S7;
end
S7:
begin
clk2 <= ~clk2;
state <= S8;
end
S8:
begin
clk2 <= ~clk2;
clk4 <= ~clk4;
fetch <= ~fetch;
state <= S1;
end
idle: state <= S1;
default: state <= idle;
endcase
end
endmodule
//--------------------------------------------------------------------------------

Since the synchronous state machine design method is adopted in the design of the clock generator, not only the source code of the clk_gen module can be synthesized by various synthesizers, but also the clk1, clk2, clk4, fetch, and alu_clk generated by it have obvious improvements in the jump time synchronization performance, laying a good foundation for improving the performance of the entire system.
Such a clock generator is perfect in both timing and function, no wonder it has been used in CPU design.