Design of inter-line transfer area array CCD driving circuit based on FPGA

1. Introduction

Charge-coupled device (CCD) is a photoelectric conversion image sensor that directly converts image signals into electrical signals. Due to its many advantages such as high integration, low power consumption, low noise, high measurement accuracy, and long life, CCD has been widely used in precision measurement, non-contact non-destructive testing, document scanning, and aerial remote sensing [1]. Array CCD imaging devices are divided into three types: full-frame transfer (FullFrame) CCD, frame transfer (Frame.Transfer) CCD, and interline transfer (InterlineTransfer) CCD. The imaging area and storage area in the interline transfer CCD are staggered in columns, so no mechanical shutter is required, the speed is the fastest, and continuous imaging can be achieved; at the same time, in the real finished product, a microlens is added to each pixel to make up for the disadvantage of a small fill factor. Typical consumer-grade cameras generally use interline transfer CCDs.

CCD devices require driving pulse signals to work properly, and the driving circuit provides the required timing logic and related voltage signals for CCD, so the development of the driving circuit is very important. The driving circuit of CCD is mainly composed of three parts: power supply module, driver circuit and driving timing generation circuit. Several commonly used CCD driving timing generation methods include: small and medium-scale digital logic circuit driving method, using read-only memory method, microprocessor or digital signal processor (DSP), using programmable logic devices, CPLD or FPGA, etc. In this article, the driving timing is realized by the third method of programmable logic device FPGA.

2. KodakCCDKAI-0340 Introduction

KAI-0340 is an interline transfer type area array CCD produced by Kodak. Single or dual channel output is optional (single channel output mode is selected in this article). The main performance parameters are as follows:

Both horizontal and vertical are driven in two phases, one of which is a three-level vertical transfer clock

Electronic shutter

Low dark current, high sensitivity

Each row has 24 dark pixels on both ends, which can be used as dark level reference

3. CCD power supply module

In order to ensure the normal operation of CCDKAI-0340S, the specific requirements for the driving voltage and DC bias voltage are shown in Table 1.

The driving clocks of the area array CCDKAI-0340S are divided into four types: horizontal shift clock, reset clock, vertical transfer clock, and electronic shutter clock. The specific requirements for the required driving voltage are shown in Table 1.

In the single-ended output mode of CCD, the pin connection of the horizontal shift clock corresponding to the image sensor is as follows: H1 = H1S (5) + H1BL (4) + H2BR (9); H2 = H2S (7) + H2BL (3) + H1BL (8). H1, H2, and R share a 74AC04 driver. Each clock uses two gate drivers, and combined with filter capacitors and clamping circuits, the horizontal and reset drive of the array CCD can be realized.

Vertical transfer requires two-phase drive clocks, V1 and V2, where V2 is a three-level clock. Since the signal generated by FPGA has only two states, '0' and '1', the signal V2 needs to be decomposed into two signals, V2HM and V2ML. V1 is driven by an EL7212, with filter capacitors and clamping circuits.

The V2 driver uses a MAX4426, and controls its power supply terminal through V2HM (reverse V2HM). When V2HM is high, MAX4426 generates a peak-to-peak output signal of 9V. When V2HM changes from high to low, the power supply terminal of MAX4426 is increased to 18V, thereby generating a three-level signal V2 that meets the requirements. The electronic shutter pulse voltage is VAB~VAB+40V (peak-to-peak value is 40V), which is generated using discrete components. The schematic diagram of the specific circuit is shown in Figure 2.

KAI-0340S requires 6 driving signals to work: two-phase horizontal shift register clocks H1 and H2; reset pulse clock RL; two-phase vertical transfer clocks V1 and V2 (decomposed into V2HM and V2ML); electronic shutter clock SUB. A working cycle of CCD imaging is divided into three stages: exposure stage, inter-line transfer stage and horizontal shift stage. When CCD is working, first the electronic shutter pulse appears at the bottom layer to clear the charge in the photosensitive area. After the electronic shutter pulse, the image signal integration stage begins. After the integration is completed, the high level on V2 transfers the charge packet containing image information in the photosensitive area to the light-blocking vertical CCD. Next, the charge packets in the vertical CCD are transferred to the horizontal CCD line by line through the complementary clocks of V1 and V2, and then the charge packets on the horizontal CCD are transferred to the floating diffusion output node one by one through the complementary clocks of H1 and H2. The charge measurement is carried out for subsequent circuit processing, and the CCD can also expose the next frame of the image. The detailed driving timing relationship of KAI-0340S can be found in its instruction manual. The procedures for implementing H1 and H2 are as follows:

The innovation of this paper is: first decompose the three levels of V2, then cleverly use two drivers and clamping circuits to realize the timing drive of the three-level step waveform; use FPGA devices to design the inter-row transfer area array CCD drive timing. After the system design is completed, the oscilloscope tests the drive signals of each output, and the displayed waveform is consistent with the simulation waveform, and a satisfactory result is obtained. Therefore, the drive circuit design scheme of this paper can meet the performance requirements of KAI-0340 and can be used to drive the inter-row transfer area array CCD KAI-0340S.