FPGA slave and fast loading solution based on CPLD

1 Common FPGA configuration methods

The configuration data of FPGA is usually stored in the memory device in the system. After power-on, the controller reads the bit file in the memory and loads it into the FPGA. There are four configuration methods: JTAG, slave-parallel, slave-serial, and master-slave. Different manufacturers have different names, but the implementation methods are basically the same.

(1) Boundary Scan JTAG Mode. The JTAG mode is commonly used in the single board debugging stage. This mode requires the JTAG interfaces of the controller, FPGA and other chips to form a daisy chain, and in this mode, other functions of the controller cannot be used.

(2) Slave-serial mode: The slave-serial loading mode takes up less resources, mainly because there are fewer I/O interfaces connected to the FPGA. However, one configuration clock can only transmit one bit of data, and the speed is relatively low.

(3) Master-slave mode. The main disadvantage of this mode is that the FLASH memory used must be the model specified by the FPGA manufacturer, and the FLASH capacity is not large and cannot be shared with the controller's FLASH. Using this mode, there will be two FLASH on a single board, increasing product cost. Therefore, this solution is rarely used.

(4) Parallel mode, which is the FPGA loading scheme discussed in this article.

2 Implementation of the parallel loading method

Taking Xilinx's Spartan-6 series FPGA as an example, the pins related to slave and load are shown in Table 1.

Table 1 Load pin names from

As can be seen from Table 1, the parallel loading interface occupies a lot of pin resources. Even if the loading data bus uses 8 bits, 14 pins are required. CPUs generally do not have so many general-purpose input/output (GPIO) ports, so parallel loading is generally used in conjunction with CPLD. The loading process is shown in Figure 1.

Figure 1 SPARTAN-6 loading process

3 FPGA loading scheme based on CPLD

3.1 Solution Introduction

In device-side communication products, the CPLD-based FPGA slave and load frame is shown in Figure 2. The configuration data is stored in FLASH, and before loading the data, the CPU moves the configuration data from FLASH to the DDR particles through the local bus and double-speed memory (DDR) interface; when it is really needed to be loaded, the configuration data is moved to the CPU cache through the DDR2 interface. The DDR2 interface is very fast, and its clock frequency can reach 266 MHz, so the loading time of steps ① and ② can be ignored.

Figure 2 CPLD-based FPGA slave and load frame

After that, the CPU writes the configuration data into the register of the CPLD byte by byte through the interface ③ with the CPLD, the 8-bit local bus interface. Taking the MIPS series CPU XLS408 as an example, the working clock frequency of XLS408 is 66.7 MHz, and the fastest write bus cycle requires 10 working clock cycles, that is, 6.67 MHz. This step is limited by the local bus speed.

After the data is written into the CPLD, it is then loaded into the FPGA through interface ④ -- the slave-parallel interface between the CPLD and the FPGA. The slave-parallel interface is a synchronous bus, and the loading time is limited by the bus clock CCLK frequency.

The advantages of this solution are: ① and ② can be processed before loading, and the running speed is fast, which does not take up the loading time. The loading time is only limited by ③ and ④, and ③ is limited by the write bus cycle interval, and ④ is limited by the clock of the slave parallel interface.

3.2 Program Implementation

The CPLD slave program is implemented in Verilog language, and the loading module interface is defined as follows:

The program implementation flow is shown in Figure 3.

Figure 3 Program flow based on CPLD from and loading FPGA

The FPGA chip selection and write signal generation code are as follows:

4 Simulation and loading results analysis

Based on the modelsim 6.5SE simulation waveform, it can be seen that the CPU needs to write the loaded data to the CPLD once every time it loads 1 byte of data, which takes a total of one local bus cycle. The fastest local bus frequency is 6.67 MHz. Therefore, the total time required for the CPU to load 4.125 MB of data to the CPLD is:

CPLD needs 1 CCLK cycle to write 1 byte of data to FPGA. CCLK is generated by the write signal of CPU local bus, which can realize the synchronization of CCLK and data. Therefore, the CCLK clock rate is 6.67 MHz. Therefore, the total time required to load 4.125 MB of data to FPGA is:

It takes 1 ms to power on the FPGA. Therefore, when the FPGA uses the highest-end 6SLX150T in the SPARTAN-6 series, the CPLD-based slave-parallel loading method is used, and the total loading time is 1.221 s, which meets the requirement of less than 2 s for the FPGA loading time of communication products. If the slave-serial loading method is used, and the ARM7 processor is used as the controller, for the EP2C35 in the CycloneII series, the configuration file size is 1.16 MB, and the loading time is 1.30 min; using the CPLD-based slave-serial loading method, loading the same 4.125 MB of FPGA data, the CPLD loading clock is 33MHz, and the loading time is 3.8 s. If the FPGA loading time is too long, it will affect the system startup time.

Table 2 is a comparison of the time required to load 6SLX150T model FPGA chip data using common loading methods.

Table 2 FPGA loading time comparison

From the above analysis, it can be concluded that if the CPU's local bus write speed is increased, the time to load the FPGA will be faster.

5 Conclusion

Compared with other loading methods, the CPLD-based FPGA parallel loading solution has an increased number of loading pins, but the loading time is greatly shortened. Moreover, if the write speed of the CPU local bus is increased, the loading speed can be further improved, which meets the requirements of fast startup of the communication system and has high practical value.