IAR Systems develops new tools for RISC-V

IAR Systems, a supplier of software tools and services for embedded development, has released a new version of IAR Embedded Tools for RISC-V. Version 1.20 adds support for the basic instruction set RV32E, as well as standard extensions for Atomic operations.

Through optimization technology, IAR Embedded Workbench helps developers ensure that applications meet the required requirements and optimize the utilization of onboard memory. Version 1.20 adds support for the basic instruction set RV32E, which targets smaller embedded devices and has a register set reduced to half of the available registers in RV32I. The standard extension of Atomic operations adds instructions that support Atomic read, modify, and write operations to support synchronization between different hardware processes accessing the same memory.

RISC-V is a free, open instruction set architecture (ISA) based on the established principles of reduced instruction set computing (RISC).

IAR Systems will exhibit at the RISC-V Summit, which will be held in San Jose, California, from December 10 to 11. It will demonstrate IAR Embedded Workbench for RISC-V.