How to control IC power consumption

Power consumption has become a critical parameter in many designs. In high-performance designs, excessive power consumption above critical temperature can impair reliability. It manifests itself as voltage droop on the chip, and can even affect timing because the on-chip logic is no longer operating at ideal voltage conditions. To address power consumption, designers must establish power-sensitive methodologies to address power throughout the chip design process.
Interconnects are beginning to dominate switching power consumption, just as they dominated timing in previous process nodes. The figure on the right shows the relative impact of interconnects on total dynamic power consumption. Today, designers have the ability to reduce power consumption through routing optimization.
Designers can also find more opportunities for automatic power reduction during the physical design phase. Automatic power reduction during physical design will complement power reduction earlier in the design process and during logic synthesis.
Power consumption is an "equal opportunity" issue: from early design trade-offs to automatic physical power optimization, all power reduction techniques complement each other and need to be considered as part of every modern design process. Engineers can apply the following guidelines as an integral part of any design methodology when addressing power consumption.

Understand that power consumption is as important a design parameter as the performance (timing), functionality, and cost of your design. Consider power consumption when making design decisions and tradeoffs. Smart design decisions early in the process can result in substantial power savings. However, it is more difficult to automatically reduce power consumption in the early stages of the design process.
Employ advanced design techniques to reduce power consumption, such as voltage/power island partitioning, block-level clock gating, power-down modes, efficient memory configuration, and parallelism. Advanced abstraction techniques that can reduce power consumption include dynamic voltage and frequency scaling, memory subsystem partitioning, voltage/power island partitioning, and software-driven sleep modes.
Accurately estimate power consumption at the RTL and pre-RTL levels. It is the designer's task to understand the design factors and specifications that affect overall power consumption, but advanced power estimation tools can be helpful in providing the designer with the information they need to make appropriate tradeoffs.
Investigate all opportunities to automatically reduce power consumption without affecting timing or increasing area. For example, register clock gating can be used effectively during the logic synthesis stage, but doing so may cause timing and signal integrity issues during the physical design process. An alternative approach is to implement clock gating during the physical design phase, when accurate timing and signal integrity information is available.
Reduce capacitance at high-power nodes by optimizing interconnects during the physical design phase, thereby saving power. Once interconnect capacitance is reduced, the logic gates driving these lower capacitance loads can be smaller or optimized to produce lower power. Reducing leakage power by replacing multiple threshold voltage cells can also be effectively implemented at the physical level.
You should not wait until almost tape-out to start worrying about power. If you do, you may find that you have done too little, too late to reduce power.
Ignore any one power-consuming factor. For example, when you are trying to reduce switching power, leakage power may be the more important component. Excessive peak power consumption can cause large noise spikes both on-chip and off-chip.
Believe that reducing the supply voltage or using a smaller geometry process will solve the power problem. Lower supply voltage reduces noise margins and slows circuit operation, making it difficult to achieve timing closure or even meet functional specifications. At 90nm and below, leakage currents are higher.
Expecting a “push-button” low-power solution or approach. Power management must be implemented at all stages of the design process—sometimes requiring design decisions, sometimes more automated.
Thinking that power-sensitive design and automatic power reduction are mutually exclusive. Both techniques will effectively help you overcome power challenges if combined in a complete power management design methodology.