Design and Application of Clock Frequency Synchronization Based on FPGA

Introduction
Networked motion control is the development trend of motion control in the future. With the development of high-speed machining technology, higher requirements are put forward for the time synchronization accuracy between network nodes. For example, in papermaking machinery, the operating speed is 1500-1800m/min. The time synchronization error of 1μs between synchronously running motors will cause a motion error of 30μm. When the processing speed in the high-speed machining center is 120m/min, the time synchronization error of 1μs between servo motors will cause a processing error of 2μm, affecting the improvement of processing accuracy.
The clock of the node in the distributed network is usually implemented in the form of crystal oscillator + counter. Due to the accuracy and stability of the crystal oscillator itself, the error of time operation is caused. Clock synchronization usually selects one node clock as the master clock and the other node clocks as slave clocks. The master node periodically sends the master clock time to the slave node through a message. After receiving the message, the slave node uses the master clock as the reference for delay compensation, and then assigns the calculated new clock value to the slave clock. This synchronization method causes discontinuity in the slave clock count value, that is, repetition (slave clock crystal frequency is faster than master clock) or jump (slave clock crystal frequency is slower than master clock), and this method does not fundamentally solve the problem of clock frequency asynchrony, so it is difficult to further improve the synchronization accuracy. This paper studies a clock that can dynamically adjust the frequency, and through the dynamic correction of the clock frequency, the master and slave clock frequencies are synchronized, thereby achieving time synchronization.

1 Clock synchronization principle
To achieve synchronization between two clocks, the clock count values ​​must be the same and the count growth rate must be the same. As shown in Figure 1, let the master clock frequency be f, the slave clock frequency be fn-1 in the time period from Nn-1 to Nn, and fn in the time period from Nn to Nn+1. SyncDelay is the delay time of the synchronization message from the master station to the slave station, which can be measured by the round-trip method using the delay measurement frame. The slave clock must be equal to the master clock at time Nn+1, so:

Because the master clock periodically sends synchronization messages, Mn+1-Mn=Mn-Mn-1=T. From equations (2) and (3), we can get:

kn is the clock frequency adjustment coefficient. The frequency adjustment coefficient can be calculated in each synchronization cycle, and then the frequency adjustment can be achieved through the corresponding hardware circuit.

2 Adjustable frequency clock design
The adjustable frequency clock is a clock counter composed entirely of digital circuits. It has a simple structure and can be easily implemented in FPGA. The principle is shown in Figure 2. The frequency adjustable clock consists of a q-bit clock counter, a q-bit accumulator, and an r-bit frequency compensation value register. In each crystal oscillator cycle, the accumulator is added to the FreqCompValue in the frequency compensation register, and the result is saved to the accumulator. If the accumulator overflows, the value of the clock counter increases by 1; otherwise, the clock counter remains unchanged. It can be seen that the size of the crystal oscillator frequency and the frequency compensation value FreqCompValue determines the overflow rate of the accumulator and the counting frequency of the clock counter. Therefore, the clock frequency can be adjusted by adjusting FreqCompValue. In order to achieve a high-precision clock, the crystal oscillator frequency must be higher than the clock frequency. Assume that the crystal frequency is FreqOsc, the clock counting frequency is FreqClk, the frequency division ratio is DivRatio, the synchronization period is SyncInterval, and the compensation accuracy is Precision. p, q, and r can be obtained by the following formula:
DivRatio=FreqOsc／FreqClk (5)

In this system, take FreqClk as 50 MHz, FreqOsc as 60MHz, then DivRatio is 1.2. When the synchronization period is 1 s, the compensation accuracy Precision can be selected as 10-9, and the formula can be selected as r=q=32, p=64. The initial value of frequency compensation is calculated by the following formula:
FreqCompValue=2q／DivRatio=232／1．2=32d3579139413
In the clock output algorithm, this value is dynamically adjusted by the frequency adjustment coefficient:
FreqCompValuen=kn·FreqCompValuen-1 (10)

3 Implementation of frequency compensation algorithm in FPGA
From equations (4) and (10), we can get:

frequency compensation is to calculate FreqCompValuen in each synchronization cycle. FPGA provides parameterized multiplier megafunction (1pm_mult) and divider megafunction (1pm_divide), which can quickly implement the above algorithm. The principle is shown in Figure 3. Driven by the synchronization signal of each synchronization cycle, latches B and C latch the current clock reading and the clock reading of the previous synchronization cycle respectively, and input the main clock reading into adder A. After passing through subtractors E, F, multiplier G, and divider H, the new FreqCompValuen is calculated and latched into latch D under the drive of the synchronization signal. Since the intermediate calculation result needs to go through a certain clock cycle, the latch signal of latch D needs to be delayed by a certain crystal oscillator cycle. In this design, the delay is 50 FreqOsc, that is, the new frequency compensation value can be obtained in the case of <1μs.

The transmission delay SyncDelay of the synchronization message is theoretically constant, but in reality the message has jitter during transmission. Reference [3] analyzes this and points out that the longer the synchronization period, the smaller the impact of the message transmission delay jitter, so it can be ignored.

4 Experimental Verification
The master clock is implemented using a 50 MHz active crystal oscillator and used as a fixed clock; the slave clock uses a 30 MHz active crystal oscillator, which is multiplied to 60 MHz by the FPGA phase-locked loop PLL and then divided by 1.2 to achieve an adjustable frequency 50 MHz clock.

The master clock and the slave clock are interrupted at a certain time interval, and the interrupt signal is sampled by a logic analyzer to analyze its deviation. Since the resolution of the system clock is 20 ns, the logic analyzer LA1532 of Guangzhou Zhiyuan Electronics Co., Ltd. is used, and its maximum sampling frequency is 100 MHz, so the deviation measurement accuracy can reach 10 ns. Figure 4 (a) is the deviation analysis of the two clocks before synchronization. The X-axis represents the timing length of the master clock and the slave clock, and the Y-axis represents the timing deviation of the master clock and the slave clock. It can be seen from the figure that the deviation of the two clocks is about 5×10-6, that is, the deviation within 1 s can reach 5μs. Figure 4 (b) is the measurement result of the deviation of the master clock and the slave clock after synchronization. A total of 1,000 measurements were made, and the synchronization deviation within 10 ms was ±20 ns. The X-axis represents the measurement time, and the Y-axis represents the master-slave clock synchronization deviation. Figure 4 (c) is the measurement result of the deviation of the two slave clocks after synchronization. A total of 1,000 measurements were made, and the synchronization deviation within 10 ms was ±40 ns. The X-axis represents the measurement time, and the Y-axis represents the synchronization deviation between the slave clocks.

Conclusion
The time synchronization method based on clock frequency adjustment is simple to implement and does not require complex software synchronization protocols. It can achieve high-precision clock synchronization by occupying a small network bandwidth and only requires low-cost FPGA support in hardware.