Design and simulation of QPSK modulation and demodulation technology system based on VHDL

QPSK modulation technology occupies a very important position in digital communication modulation technology. Combining communication technology with FPGA is an inevitable trend in the development of modern communication technology. QPSK technology has the advantages of strong anti-interference performance, good bit error performance, and high spectrum utilization. It is currently widely used in digital communication, digital video broadcasting, digital satellite broadcasting and other fields. This paper introduces the working principle of QPSK technology in detail, completes the system design of QPSK modulation and demodulation, and writes the modulation and demodulation program in VHDL language. The module and program are simulated by QuartusⅡ software , and downloaded to the FPGA chip EP1K30TC144-3 through pin locking. The software simulation and hardware verification results show the correctness and feasibility of the design.

1 Design of QPSK modulation and demodulation system based on FPGA

Quaternary absolute phase shift keying ( QPSK or 4PSK) uses four different phases of the carrier to represent digital information. Since each carrier phase represents two bits of information, each quaternary code element can be represented by a combination of two binary code elements (often called a two-bit code element), which is generally arranged in Gray code. The implementation principle block diagram of modulation and demodulation is shown in Figure 1. As shown in Figure 1, the circuit is mainly composed of a frequency divider and a four-to-one switch. The frequency divider divides and counts the external clock signal and outputs four coherent digital carrier signals with the same frequency but different phases; the crystal oscillator and the frequency division and phase shift circuits respectively send out four different phases of carriers required for phase modulation. According to the different two-bit code elements output by the serial/parallel converter, the logic phase selection circuit outputs the corresponding phase of the carrier. The four-to-one switch selects the four carrier signals under the control of the baseband signal and outputs a digital QPSK signal. However, this is not a true QPSK signal. A D/A converter needs to be added outside the FPGA device to convert the output into an analog signal.

Since the QPSK signal can be regarded as the synthesis of two carrier orthogonal 2PSK signals, the demodulation of the QPSK signal can be carried out using a demodulation method similar to that of the 2PSK signal. In general, coherent demodulation is used to obtain a better demodulation effect. 2 QPSK digital modulator simulation

There are two methods for generating QPSK signals: phase selection method and orthogonal modulation method. In this design, we use the phase selection method. The specific relationship is shown in Table 1.

Input clock signal clk and enable signal start. QPSK modulation is performed only when start is high, and the input baseband signal is converted from serial to parallel. The baseband signal x is converted from one signal to two parallel signals, which are a signal and b signal respectively after conversion. Then the ab signal constitutes a two-bit parallel signal yy. The converted yy value is shown in Table 1. The clock signal enters the eight-frequency counter q for frequency division to obtain four carriers with different phases. The four carriers have phases of 45°, 135°, 225°, and 315°. The four-to-one switch selects the corresponding phase of the carrier for output according to the signal yy value, and the modulated signal Y can be obtained. As shown in Table 1, when the yy value is "0", the corresponding carrier f3 is selected for output; when the yy value is "01", the corresponding carrier f2 is selected for output; when the yy value is "10", the corresponding carrier f1 is selected for output 3; when the yy value is "11", the corresponding carrier fo is selected for output, that is, the carrier waveform finally selected for output constitutes the modulated signal Y. When start is high, modulation is performed. When the input baseband signal is 1011 00 01 10 11 10 00 00 00, the simulation results are shown in Figure 2. The selected phases are 315°, 45°, 225°, 135°, 315°, 45°, 315°, 225°, 225°, 225°. The VHDL program of the QPSK modulation structure is as follows:

3 QPSK digital demodulator simulation

According to the demodulation principle, the VHDL model of the MPSK demodulation circuit is shown in Figure 1. The clock signal clk and the enable signal start are input. MPSK demodulation is performed only when start is high. The modulated signal x is input. The input phase is 225°, 315°, 45°, 225°, 135°, 315°, 45°, 315°, 225°, 225°, 225°, 315° of the carrier waveform. One signal cycle is divided into 4 parts. The high level weights are 0, 0, 0, 0 respectively. The low level weights are 1, 1, 2, 3 respectively, as shown in Table 2.

As shown in Figure 1, when the modulation signal x is at a low level, decoder 1 sends the corresponding data to adder XX according to the counter q value. After repeated operations, when the q value is 0 and 1, adder xx sends the operation result to the register. Decoder 2 decodes according to the yy data and outputs a 2-bit parallel signal YYY. As shown in Table 2, the relationship between the intermediate signal yy and YYY is: 5 corresponds to "00"; 3 corresponds to "01"; 2 corresponds to "10", and 4 corresponds to "11". The parallel signal YYY is converted to a Y value after parallel/serial conversion. Finally, a carrier with a phase of 225° is realized, and the corresponding output Y value is "00"; a carrier with a phase of 135° corresponds to an output Y value of "01"; a carrier with a phase of 315° corresponds to an output Y value of "10"; a carrier with a phase of 45° corresponds to an output Y value of "11". When the start signal is high, the demodulated signal begins, and the output result (y) is 0010 11 00 01 10 11 10 00 00 00 10. The simulation results are shown in Figure 3.

4 Conclusion

This paper implements the design of QPSK digital modulation and demodulation circuit based on VHDL . The program is simulated through QuartusII software modeling , and downloaded to FPGA chip EP1K30TC144-3 through pin locking. The software simulation and hardware verification results show the correctness and feasibility of the design. Compared with the traditional circuit design, it has obvious advantages, simplifies the design, reduces the complexity of the hardware circuit, and improves the flexibility and portability of the design due to the use of FPGA chips, reduces the complexity of hardware design, and facilitates transplantation, maintenance and upgrade. For example, in order to prevent phase ambiguity, differential encoding is used, and the QDPSK modulation and demodulation system is used, and only the software program needs to be changed.