Verilog HDL hardware description language basic training

Overview of Verilog HDL hardware description language
Top-down design philosophy of Verilog HDL
Whether to choose Verilog or VHDL
What is the use of Verilog HDL
How to avoid competition and risks Examples of writing and verification of
behavioral-level and RTL-level Verilog modules ModelSim and Quartus using Verilog modules What are the  basic components of Verilog HDL? The difference between reg and wire in Verilog. Blocking and non-blocking in Verilog. Two different assignment statements in Verilog.

• Chapter 1：Verilog HDL Hardware Description Language Overview (5 minutes and 22 seconds)

• Chapter 2：Verilog HDL top-down design philosophy (10 minutes and 5 seconds)

• Chapter 3：Should I choose Verilog or VHDL? (13 minutes and 15 seconds)

• Chapter 4：What are the uses of Verilog HDL (6 minutes and 20 seconds)

• Chapter 5：How to avoid competition and risk taking (3 minutes and 42 seconds)

• Chapter 6：Behavioral and RTL levels (9 minutes and 52 seconds)

• Chapter 7：Examples of writing and verification of Verilog modules (19 minutes and 25 seconds)

• Chapter 8：Use of ModelSim and Quartus (35 minutes and 19 seconds)

• Chapter 9：The basic building blocks of Verilog modules (22 minutes and 14 seconds)

• Chapter 10：What are the uses of Verilog HDL (6 minutes and 20 seconds)

• Chapter 11：The difference between reg and wire in Verilog (8 minutes and 11 seconds)

• Chapter 12：Blocking and non-blocking in Verilog (6 minutes and 17 seconds)

• Chapter 13：Two different assignment statements in Verilog (6 minutes and 1 seconds)