VHDL Design and Implementation of Digital Voltmeter

In the field of hardware electronic circuit design, electronic design automation (EDA) tools have become the main design means, and VHDL language is one of the key technologies of EDA. It adopts a top-down design method, that is, starting from the overall requirements of the system, the design task is decomposed into different functional modules from top to bottom, and finally the functional modules are connected to form a top-level module to complete the overall design of the system hardware. This article uses FPGA chips and VHDL language to design a digital voltmeter , and illustrates the process of using VHDL language to realize digital systems.

The hardware structure of the entire digital voltmeter is shown in Figure 1.

When working, the system collects the input analog voltage at a certain rate , converts it into an 8-bit digital quantity through ADC 0804 , and the 8-bit digital quantity is processed by FPGA to obtain the digital code of the analog voltage, which is then input into the digital tube to obtain the digital display of the measured voltage.

The measuring range of this voltmeter is 0～5V, with three-digit digital tube display.

The three major modules of the digital voltmeter are all implemented using VHDL language programming.

2.1 Control Module

The state machine is used to generate the chip select signal and read/write control signal of ADC0804, and the state signal INTR is used to determine whether the conversion is completed; after the conversion is completed, the conversion data is latched and output. The state transition diagram is shown in Figure 2.

ADC0804 is an 8-bit analog-to-digital converter . It has 28=256 output states. If the input signal Vin is in the voltage range of 0~5V, the value of each two states is 5/(256-1), which is about 0.0196V, so the measurement resolution is 0.02V. The commonly used measurement method is: when the DB7~DB0 conversion value is XXH, the voltage measurement value is U≈XXH×0.02V; considering that directly using multiplication to calculate the corresponding voltage value will consume a large number of FPGA internal components, this design uses a table lookup command to get the correct voltage value.

After reading the conversion data of ADC0804, first use the table lookup instruction to calculate the high and low 4-bit voltage values, and express them in 12-bit BCD codes respectively; then design the 12-bit BCD code addition, if the result of each 4-bit addition exceeds 9, add 6 to adjust it. In this way, the BCD code of the analog voltage is obtained.

The functional simulation results of this module are shown in Figure 3; when the conversion data is 00010101, by looking up the table, the upper 4 bits 0001 are 0.32V, and the lower 4 bits 0101 are 0.1V. The final voltage output result is 0.32V+0.1V=0.42V. Its BCD code is 000001000010, and the simulation result is correct.

2.3 Scanning and display module

As shown in Figure 4, CLK is the scanning clock with a frequency of 1kHz, which is obtained by dividing the given 40MHz clock; DATAIN is the BCD code of the voltage value output by the data processing module; SEL is the chip select signal of the digital tube; POINT is the decimal point drive of the digital tube; the BCD code DATAOUT of the 3-digit voltage value is output by scanning, and the BCD code is translated into the corresponding 7-segment digital drive value through DISP and sent to the digital tube for display.

The VHDL language program designed in this paper has been compiled, simulated and debugged on the MAXPLUSⅡ tool software, and downloaded to the EP1K100QC208-3 chip through the programmer. After experimental verification, this design is correct, and its voltage display value error does not exceed the upper limit of the quantization step (0.02V). The design ideas given in this paper are also applicable to other system designs based on PLD chips.