FPGA realizes digital tube counting

littleshrimp

FPGA realizes digital tube counting [Copy link]

 

The function is similar to the counter in the mall where you can get a gold bar if you press the button for 10 seconds. Since there is no button, a switch is used instead. It is recommended that the manufacturer put a button on the board. The function is to start counting when the switch is turned up, and stop counting and display the current value when it is turned down.

The code is written by myself, and the segment selection of the digital tube uses the data of @怀揣少年梦, https://en.eeworld.com/bbs/thread-1189456-1-1.html.

Because I am a novice in FPGA, the function can be realized, but I don't know whether the design is reasonable. If there are FPGA experts who find problems, I hope they can give me more advice. The project file is at the bottom of this article.

I also found a problem when adding comments. During synthesis, an error like "ERROR (EX3863) : Syntax error near '<='("C:\Users\lu\Documents\fpga_project_3\src\top.v":34)" was prompted, but I didn't find the problem in the code.

Later I found that it can work normally if I remove this comment, or if I leave a blank line between the comment and the code. I think this is a rather strange phenomenon and I can't explain it at the moment. Interested netizens can help analyze it.

Part of the code:

module top(
    input clk,                              //50MHz时钟输入
    input sw,                               //开关输入
    output reg[7:0]seg,                     //数码管输出
    output reg[3:0]sel                      //数码管位选
);
wire cnt_clk;                               //计数时钟
wire rfs_clk;                               //刷新时钟

reg[1:0] bcd_index = 2'b0;                  //计数位选(0=个位...3=千位)
wire[3:0] bcd_out;                          //指定位的数值（0~9）
reg[18:0] cnt = 19'b0;                       //计数                      
reg [3:0] bcd[0:3];                         //要输出的数位数组，[0=个位...3=千位][0~9]

//判断开关状态，决定是否更新计数
always@(posedge clk) begin
    if(sw)begin
        bcd[bcd_index] = bcd_out;
    end
end
//cnt计数
always@(posedge clk) begin
    if(cnt == 50_000 - 1)
        cnt <= 19'b0;
    else
        cnt <= cnt + 1'b1;
end
//根据cnt计数更新位选索引
always@(posedge clk) begin
    if(cnt == 0)
        bcd_index <= bcd_index + 1'b1;
end
//根据位选索引控制对应的数据管位选引脚，低电平为选中

always@(posedge clk) begin
    case(bcd_index)
        4'd0:sel <= ~4'b0001;
        4'd1:sel <= ~4'b0010;
        4'd2:sel <= ~4'b0100;
        4'd3:sel <= ~4'b1000;
    endcase
end
//将bcd值转换成对应的数码管段的控制数据
always@(posedge clk) begin
    case(bcd[bcd_index])
        4'd0:seg = 8'hc0;
        4'd1:seg = 8'hf9;
        4'd2:seg = 8'ha4;
        4'd3:seg = 8'hb0;
        4'd4:seg = 8'h99;
        4'd5:seg = 8'h92;
        4'd6:seg = 8'h82;
        4'd7:seg = 8'hf8;
        4'd8:seg = 8'h80;
        4'd9:seg = 8'h90;
        default:seg = 8'hc0;
    endcase
end
//时钟分频
clk_div clk_div_ins(
    .clk(clk),
    .clk1(cnt_clk),
    .clk2(rfs_clk)
);
//4位bcd计数,cnt_clk是计数时钟，rfs_clk时钟决定输出bcd_index对应数位的数值
bcd4 bcd4_ins(
    .cnt_clk(cnt_clk),
    .read_clk(rfs_clk),
    .bit_index(bcd_index),
    .bcd_out(bcd_out)
);
endmodule

Project Files:

fpga_project_3.rar (105.75 KB, downloads: 0)

2021-12-18 15:45 上传

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raymond0925

good

Fred_1977

Good, I am still learning.