Implementation of fourth-order IIR digital filter circuit design using FPGA

A fourth-order IIR digital filter is implemented using FPGA, and a digital elliptical low-pass filter is formed by cascading two second-order sections. The ripple in the passband is less than 0.1dB, and the stopband attenuation is greater than 32dB. Commonly used digital filters include FIR digital filters and IIR digital filters. The FIR digital filter has precise linear phase characteristics and is widely used in signal processing. The design can be completed using the pre-designed and debugged FIR digital filter IP Core. In addition, for the same design indicators, the order required by the FIR filter is 5 to 10 times higher than that of the IIR filter, the cost is higher, and the signal delay is also larger. The required order of the IIR filter is not only lower than that of the FIR filter, but also the design results of the analog filter can be used, and the design workload is relatively small. The IIR filter implemented using FPGA also has many advantages.

The digital filter is actually a linear non-time-varying discrete system implemented using a limited precision algorithm. Its design steps are: first determine its performance indicators according to actual needs, then obtain the system function, and finally implement it using a limited precision algorithm. According to the needs, the design indicators of this system are: the sampling frequency of the analog signal is 2MHz, and the minimum sampling point is 20 points per cycle. That is, the passband edge frequency of the analog signal is fp=100kHz, the stopband edge frequency=1MHz, and the passband fluctuation is not greater than 0 . 1dB (passband error is not greater than 5%), stopband attenuation A s is not less than 32dB. It is more convenient to use Matlab software to calculate system functions.

This article uses a compromise method to implement it, that is, the multiplier of the multiply-accumulate unit (MAC) uses an array multiplier instead of a serial multiplier to improve the operation speed. It should be noted that the multiplication operation in the LPM library of MAX+plus II is unsigned array multiplication, so when using it, you need to first convert the two complement multipliers into unsigned numbers and then multiply them, and then convert the product into complement Code product output. It takes a total of 6 clock cycles for each second-order section to complete an operation, and independent MACs need to be used to implement a two-stage pipeline structure, that is, each data needs only 6 clock cycles to be output through two second-order sections.