How does Anlu FPGA output the clock to ordinary IO?

1nnocent

How does Anlu FPGA output the clock to ordinary IO? [Copy link]

 

 

Now I want to output the clock generated by the PLL IP core to a normal IO pin using the ODDR primitive, but the compiler software shows missing file!!!

This is the IP core that used the PLL of Xilinx FPGA to generate the clock, and output the clock to the ordinary IO pin through the ODDR primitive. It has been verified to be usable on vivado before, but it seems that it cannot be used on Anlu's TD software.

1. How can Anlu FPGA output the clock to the ordinary IO pin?

2. How to input external clock into IO pin? When I used Xilinx before, there was syntax to achieve it when constraining pins, but I don’t know how to achieve it on Anlu.

nmg

Anlu Technology looked at it and felt that your oddr looked like it was copied directly from another platform. The name was wrong, so the module could not be found. They have IP support, named EG_LOGIC_ODDR, which can be generated through the IP interface or directly instantiated. You can try it.

1nnocent

nmg posted on 2022-7-28 15:01 Anlu Technology looked at it and felt that your oddr looked like it was copied directly from another platform. The name was wrong, so it couldn't find this module. He...

Thank you very much. I copied this from Xilinx. My previous development boards all used Xilinx FPGA. If the clock is input from IO, do I need to instantiate IDDR?

bigbat

1. First find the physical clock pin of Anlu.

2. Instantiate a PLL module

3. Introduce the physical clock pin into the PLL module

4. Lead the PLL module output pin to the destination physical pin

bigbat

From your question, it seems that you don't understand what FPGA is at all, and you seem to mistake FPGA for a microcontroller.

1nnocent

bigbat posted on 2022-7-28 16:27 From your question, it seems that you don’t understand what FPGA is for at all, and you seem to be mistaking FPGA for a microcontroller.

Do you think that the PLL clock output can directly constrain the physical IO?

bigbat

1nnocent posted on 2022-7-28 16:35 Do you think that the PLL clock output can directly constrain the physical IO?

I want to ask you whether a register can flip according to the clock, and whether a register can output the status to the physical IO.

1nnocent

bigbat posted on 2022-7-28 16:26 1. First find the physical clock pin of Anlu, 2. Instantiate a PLL module 3. Introduce the physical clock pin into the PLL module 4. Put the PLL module...

https://blog.csdn.net/weixin_42483560/article/details/125643424

littleshrimp

bigbat posted on 2022-7-28 16:43 I want to ask you whether a register can flip according to the clock, and whether a register can output the state to the physical IO.

In Xilinx FPGA, the output clock must use ODDR, because the clock output is not a simple flip, but also involves delay and jitter issues.

1nnocent

bigbat posted on 2022-7-28 16:43 I want to ask you whether a register can flip according to the clock, and whether a register can output the state to the physical IO.

https://blog.csdn.net/qq_37145225/article/details/99657486

The clock is output through ordinary IO, including the clock input from IO to FPGA, which is not simply directly constrained to the corresponding signal

bigbat

littleshrimp posted on 2022-7-28 16:47 In Xilinx FPGA, the output clock does use ODDR, because the clock output is not a simple flip, but also involves delay and jitter issues.

I know that real clock signals are very complex. I mean, using clock signals to operate registers, can we output the status of the registers?

bigbat

littleshrimp posted on 2022-7-28 16:47 In Xilinx FPGA, the output clock does use ODDR, because the clock output is not a simple flip, but also involves delay and jitter issues.

Because the OP did not mention using the primitive clock signal

littleshrimp

1nnocent posted on 2022-7-28 15:06 Thank you very much. I copied this from Xilinx. The development boards used Xilinx FPGA before. If the clock is input from IO, it is...

The IDDR used in xilinx can be generated by IP or by using EG_LOGIC_IDDR.

1nnocent

littleshrimp posted on 2022-7-28 17:20 The IDDR used in xilinx can be generated by IP or EG_LOGIC_IDDR.

OK, thank you very much. It's easy to handle if you know where the stuff is. When I wrote this code myself, I could hardly find any code using TD on the Internet.

littleshrimp

1nnocent posted on 2022-7-28 17:49 OK, thank you very much, it is easy to deal with it once you know where the things are. When I wrote this code myself, I could hardly find any code using TD on the Internet

The information on the Internet is indeed not as much as that of Xilinx. Have you read the software manual of TD?

1nnocent

littleshrimp posted on 2022-7-28 18:02 The information on the Internet is indeed not as much as that of xilinx. TD has a software manual. Have you read it?

I did look at it. I downloaded it from the post you posted. It can also be found in the software help. At that time, I thought that ODDR was not classified as an IP core (because Xilinx directly uses primitives, so I didn't look for problems in that direction); on the other hand, the progress was not yet to the IP core, so I didn't look at it carefully.

littleshrimp

1nnocent posted on 2022-7-28 18:48 I have seen it, and I downloaded it from the post you posted. It can also be found in the software help. At that time, I thought that ODDR was not classified as an IP core (because Xilinx...

I don’t know if the previous one is the latest version. The corresponding document can be found under the help menu of TD.

TD recommends using the latest version. 5.5 fixes many problems compared to 4.6. I just checked and version 5.6 has been released.

1nnocent

littleshrimp posted on 2022-7-28 19:03 I don't know if the previous one is the latest version. The corresponding document can be found under the help menu of TD. TD recommends using the latest version, 5.5 compared to 4.6 ...

I didn't pay attention to the version issue. I have always used 4.6.

littleshrimp

1nnocent posted on 2022-7-28 19:08 I really didn't pay attention to the version problem. I have always used 4.6

Try the new version. There are many unreasonable designs in 4.6.

xenbabala

littleshrimp posted on 2022-7-28 19:03 I don't know if the previous one is the latest version. The corresponding document can be found under the help menu of TD. TD recommends using the latest version, 5.5 compared to 4.6 ...

Hello, can you share the latest version of TD user manual? I can't find it online and can't download it from TD official website.