【 Domestic FPGA Anlu High Integration Low Power Consumption SF1 Series FPSoC】 Part 5 Simple Counter and D Flip-Flop Design

常见泽1

【 Domestic FPGA Anlu High Integration Low Power Consumption SF1 Series FPSoC】 Part 5 Simple Counter and D Flip-Flop Design [Copy link]

 

Design of a simple D flip-flop

The function of the D flip-flop is to send the input of the D flip-flop to the output on the rising edge of the clock (the edge of the clock is often used in the design of timing circuits, that is, the rising edge and the falling edge. The rising edge is the jump of the clock signal from low to high, and the falling edge is the jump of the clock signal from high to low).

module gate( d, q, clk);

input d;

input clk;

output q;

reg q;



always @(negedge clk )



begin

q <= d;

end





endmodule

Press to pull low

d-H3-key0

clk-H2-key1

q – J4 – LED_R

KEY1 is pressed, and a falling edge appears

The value of KEY0, if not pressed, is 1, and is sent to the LED to light up.

Press key0 and the value is 0. Release key1 and press key1 again and the LED turns off.

Design of a simple counter

As a basic device of timing circuit, counter is the simplest and most basic operation. Counter is the logic circuit that realizes this operation. In digital system, counter mainly counts the number of pulses.

module Counter(output reg [2:0] counter,

input clk,

input up_down,

input reset);



always @(negedge clk or negedge reset)begin

if(~reset)

counter <= 0;

else begin

if(~up_down)

counter <= counter + 1;



end

end

endmodule

When the button is pressed, count the number of CLK clocks

CLK is configured as KEY

UP_DOWN is configured as KEY

COUNTER is configured as 3 LED lights

When UP_DOWN is pressed, the LED lights will light up from 001 to 111 every time the CLK key is pressed.

zhaoyanhao

May I ask what development software Anlu uses?

常见泽1

zhaoyanhao posted on 2024-2-28 16:17 What development software does Anlu use?

TangDynasty software, referred to as TD