FPGA Experiment (IV) PWM Breathing Light Based on HDL Language

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FPGA Experiment (IV) PWM Breathing Light Based on HDL Language [Copy link]

 1. PWM wave breathing light (high four-bit and low four-bit light brightness comparison, fixed duty cycle)

1. module PWM_LED( input ext_clk_50M, output reg[3:0]LED ); reg [31:0]cnt; reg [7:0]num; reg div_50_clk; always @ (posedge ext_clk_50M) if (cnt == 32'd50) begin cnt <= 0; div_50_clk <= ~div_50_clk; end else cnt <= cnt + 32'd1; always @ (posedge module PWM_LED( input ext_clk_50M, input key_in, output reg[3:0]LED ); parameter s0 = 2'b00,s1 = 2'b01,s2 = 2'b10,s3 = 2'b11; reg key_out; reg[1:0]state; reg [31:0]cnt; reg [7:0]num; reg [7:0]flag; reg div_50_clk; always @ (posedge ext_clk_50M) case(state) s0: begin key_out <= 1'b1; == 1'b0) state <= s1; else state <= s0; end s1: begin if(key_in == 1'b0) state <= s2; else state <= s0; end s2: begin if(key_in == 1'b0) state <= s3; else state <= s0; end s3: begin if(key_in == 1'b0) begin key_out <= 1'b0; state < = s3; end else begin key_out <= 1'b1; state <= s0; end end default:state <= s0; endcase always @ (negedge key_out) if(flag == 8'd100) flag <= 8'd0; else flag <= flag + 8'd10; always @ (posedge ext_clk_50M) if(cnt == 32'd50) begin cnt <= 0; _50_clk <= ~div_50_clk; end else cnt <= cnt + 32'd1; always @ (posedge ext_clk_50M) if(num == 8'd100)num <= 8'd0; else num <= num + 8'd1; always @ (posedge div_50_clk) if(num > flag)LED <= 4'b0000; else LED <= 4'b1111; endmodule

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The video demonstration effect is as follows: PWM呼吸灯（状态机按键消抖PWM可调）.mp4 (1.84 MB, downloads: 4)

2019-4-26 19:19 上传

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The project file sharing is as follows: 3.1、PWM波呼吸灯(高四位和低四位对比).rar (352.29 KB, downloads: 0)

2019-4-26 19:20 上传

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3.2、PWM波（锁定特定引脚74用示波器观看）.rar (349.33 KB, downloads: 0)

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3.3、PWM波呼吸灯(按键可调).rar (402.98 KB, downloads: 0)

2019-4-26 19:21 上传

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I hope it can help you, welcome to discuss!