FPGA design ideas and verification methods video tutorial (lectured by Brother Xiaomei)

  Here, Brother Xiaomei will share with you our carefully recorded and edited series of FPGA learning tutorials - "Brother Xiaomei's FPGA Design Ideas and Verification Methods Video Tutorial". The tutorial fully considers the actual situation of 0-level friends and guides learners step by step in analyzing ideas, writing code, simulation verification, and board-level debugging. Teach grammar, learn simulation, step by step, until finally designing several more comprehensive logic systems.

  The tutorial uses our self-developed Xinxianhang FPGA learning board as the experimental platform. Through several basic and comprehensive system design explanations, we can master the ideas and methods of FPGA design and verification step by step.

• Chapter 1：Author's words_Introduction to Xinhanghang FPGA development board (1 minutes and 3 seconds)

• Chapter 2：Lesson 1 Scientific FPGA Development Process (Part 1) (19 minutes and 35 seconds)

• Chapter 3：Lesson 1 Scientific FPGA Development Process (Part 2) (40 minutes and 0 seconds)

• Chapter 4：Lesson 1 Scientific FPGA Development Process (Part 2) (19 minutes and 0 seconds)

• Chapter 5：Lesson 2 3-8 Decoder Design and Verification (46 minutes and 2 seconds)

• Chapter 6：Lesson 3 Counter Design and Verification (Part 1) (27 minutes and 1 seconds)

• Chapter 7：Lesson 3 Counter Design and Verification (Part 2) (28 minutes and 43 seconds)

• Chapter 8：Lesson 4 High Performance Counter IP Core Calling and Verification (48 minutes and 41 seconds)

• Chapter 9：Lesson 5 BCD Counter Design and Verification (53 minutes and 2 seconds)

• Chapter 10：Lesson 6 Example: Blocking assignment and non-blocking assignment (51 minutes and 54 seconds)

• Chapter 11：Lesson 7 State Machine Design Example (1 hours and 2 minutes and 50 seconds)

• Chapter 12：Lesson 8: Design and verification of button debounce module (Part 1) (1 hours and 59 minutes and 3 seconds)

• Chapter 13：Lesson 8: Introduction to key debouncing and metastability issues (Part 2) (1 hours and 33 minutes and 47 seconds)

• Chapter 14：Lesson 9 Digital tube dynamic scanning design and verification (Part 1) (1 hours and 5 minutes and 18 seconds)

• Chapter 15：Lesson 9 Digital tube dynamic scanning design and verification (Part 2) (59 minutes and 7 seconds)

• Chapter 16：Lesson 10 Serial port sending module and verification (Part 1) (1 hours and 50 seconds)

• Chapter 17：Lesson 10 Serial port sending module and verification (Part 2) (52 minutes and 53 seconds)

• Chapter 18：Lesson 11 Serial port receiving module design and verification (1 hours and 9 minutes and 52 seconds)

• Chapter 19：Lesson 12 Dual-port RAM used in embedded block RAM (44 minutes and 57 seconds)

• Chapter 20：Lesson 13: Build a simple application system for serial port transceiver and dual-port RAM access (Part 1) (1 hours and 5 minutes and 19 seconds)

• Chapter 21：Lesson 13: Build a simple application system for serial port transceiver and dual-port RAM access (Part 2) (49 minutes and 40 seconds)

• Chapter 22：Lesson 14 rom_signaltap (1 hours and 15 minutes and 4 seconds)

• Chapter 23：Lesson 15: FIFO used in embedded block RAM (Part 1) (50 minutes and 19 seconds)

• Chapter 24：Lesson 15: FIFO used in embedded block RAM (Part 2) (50 minutes and 19 seconds)

• Chapter 25：Lesson 16 Introduction and simple application of PLL phase locked loop (1 hours and 5 minutes and 34 seconds)

• Chapter 26：Lesson 17 Linear sequencer and serial interface DAC driver design (Part 1) (57 minutes and 12 seconds)

• Chapter 27：Lesson 17 Linear sequencer and serial interface DAC driver design (Part 2) (50 minutes and 14 seconds)

• Chapter 28：Lesson 18 HT6221 infrared remote control decoding (Part 1) (1 hours and 24 minutes and 0 seconds)

• Chapter 29：Lesson 18 HT6221 infrared remote control decoding (Part 2) (1 hours and 8 minutes and 15 seconds)